92 lines
3.3 KiB
Tcl
92 lines
3.3 KiB
Tcl
###############################################################################
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## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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proc init {cellpath otherInfo} {
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set ip [get_bd_cells $cellpath]
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bd::mark_propagate_only $ip \
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"AXI_ADDR_WIDTH"
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}
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# Executed when you close the config window
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proc post_config_ip {cellpath otherinfo} {
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set ip [get_bd_cells $cellpath]
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# Update AXI interface properties according to configuration
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set axi_protocol [get_property "CONFIG.AXI_PROTOCOL" $ip]
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set data_width [get_property "CONFIG.AXI_DATA_WIDTH" $ip]
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set src_fifo_size [get_property "CONFIG.SRC_FIFO_SIZE" $ip]
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set dst_fifo_size [get_property "CONFIG.DST_FIFO_SIZE" $ip]
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if {$axi_protocol == 0} {
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set axi_protocol_str "AXI4"
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set max_beats_per_burst 256
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} else {
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set axi_protocol_str "AXI3"
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set max_beats_per_burst 16
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}
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set num_m [get_property "CONFIG.NUM_M" $ip]
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for {set idx 0} {$idx < $num_m} {incr idx} {
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set intf [get_bd_intf_pins [format "%s/MAXI_%d" $cellpath $idx]]
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set_property CONFIG.PROTOCOL $axi_protocol_str $intf
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set_property CONFIG.MAX_BURST_LENGTH $max_beats_per_burst $intf
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set_property CONFIG.NUM_WRITE_OUTSTANDING $src_fifo_size $intf
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set_property CONFIG.NUM_READ_OUTSTANDING $dst_fifo_size $intf
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}
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# For multi master configurations (e.g.HBM) the AXIS data widths must match
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if { $num_m > 1} {
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set src_width [get_property "CONFIG.SRC_DATA_WIDTH" $ip]
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set dst_width [get_property "CONFIG.DST_DATA_WIDTH" $ip]
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if {$src_width != $dst_width} {
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bd::send_msg -of $cellpath -type ERROR -msg_id 1 -text ": For multi AXI master configuration the Source AXIS interface width ($src_width) must match the Destination AXIS interface width ($dst_width) ."
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} else {
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# AXIS Data widths divided by number of masters must be >= 8 and power of 2
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set bits_per_master [expr $src_width/$num_m]
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if {$bits_per_master < 8} {
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bd::send_msg -of $cellpath -type ERROR -msg_id 2 -text ": Number of AXI masters ($num_m) too high. AXIS data widths divided by number of masters ($src_width / $num_m = $bits_per_master) must be >= 8 ."
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}
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}
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}
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}
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proc log2 {x} {
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return [tcl::mathfunc::int [tcl::mathfunc::ceil [expr [tcl::mathfunc::log $x] / [tcl::mathfunc::log 2]]]]
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}
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# Executed when the block design is validated
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proc propagate {cellpath otherinfo} {
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set ip [get_bd_cells $cellpath]
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}
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proc post_propagate {cellpath otherinfo} {
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set ip [get_bd_cells $cellpath]
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#Check address space
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set length_width [get_property "CONFIG.LENGTH_WIDTH" $ip]
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set axi_addr_width [get_property "CONFIG.AXI_ADDR_WIDTH" $ip]
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set ddr_base_adddress [get_property "CONFIG.DDR_BASE_ADDDRESS" $ip]
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set hbm_segment_index [get_property "CONFIG.HBM_SEGMENT_INDEX" $ip]
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set mem_type [get_property "CONFIG.MEM_TYPE" $ip]
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if {$mem_type == 1} {
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set addr_width [log2 [expr $ddr_base_adddress + 2 ** $length_width - 1]]
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} else {
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# assumption: 1 segmetn is 256MB
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set addr_width [log2 [expr $hbm_segment_index * 256 * 1024 * 1024 + 2 ** $length_width - 1]]
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}
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set_property "CONFIG.AXI_ADDR_WIDTH" $addr_width $ip
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bd::send_msg -of $cellpath -type INFO -msg_id 2 -text ": AXI Address Width set to $addr_width"
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}
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