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Istvan Csomortani c4152627f0 plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width 
The adc_wcnt_int must be synchronized to adc_wr. The adc_dwr signal pulse width was to long,
it needs to be just one adc_clk cycle.
 		2014-12-09 13:59:19 +02:00
library plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width 2014-12-09 13:59:19 +02:00
projects ad9467_kc705: Fix typos. 2014-12-09 12:07:49 +02:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Add a link to EngineerZone 2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga