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pluto_hdl_adi/library/axi_dmac
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Laszlo Nagy c5b62a04b7 axi_dmac: fix 2d transfer address width 
The index on MSB of addresses was set to 31,
but the width of address in the axi_dmac depends on a parameter.
The mismatch causes issues in the Xilinx simulator which does not extends the
narrower width signal with zeros, instead the wider signal gets 'Z' on its MSBs.
When the address was incremented with the stride it became 'X' due the uninitialized
MSBs.
 		2018-07-12 16:53:06 +03:00
..
bd axi_dmac: Limit MAX_BYTES_PER_BURST to maximum supported value 2018-04-24 12:49:24 +02:00
tb axi_dmac: Enforce transfer length and stride alignments 2018-07-03 13:44:34 +02:00
2d_transfer.v axi_dmac: fix 2d transfer address width 2018-07-12 16:53:06 +03:00
Makefile axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
address_generator.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
axi_dmac.v axi_dmac: diagnostic interface in bursts 2018-07-10 12:30:34 +03:00
axi_dmac_burst_memory.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
axi_dmac_constr.sdc axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_constr.ttcl axi_dmac: Remove unused constraint 2018-07-06 16:31:40 +03:00
axi_dmac_hw.tcl axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
axi_dmac_ip.tcl axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
axi_dmac_pkg_sv.ttcl axi_dmac: ttcl file support for simulation 2018-07-11 11:30:22 +03:00
axi_dmac_regmap.v axi_dmac: Enforce transfer length and stride alignments 2018-07-03 13:44:34 +02:00
axi_dmac_regmap_request.v axi_dmac: Enforce transfer length and stride alignments 2018-07-03 13:44:34 +02:00
axi_dmac_reset_manager.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
axi_dmac_resize_dest.v axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_resize_src.v axi_dmac: Remove backpressure from the source pipeline 2018-07-03 13:44:34 +02:00
axi_dmac_transfer.v axi_dmac: fix 2d transfer address width 2018-07-12 16:53:06 +03:00
axi_register_slice.v
…
data_mover.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
dest_axi_mm.v axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
dest_axi_stream.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
dest_fifo_inf.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
inc_id.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_arb.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_generator.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
resp.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_generator.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_handler.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
splitter.v
…
src_axi_mm.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
src_axi_stream.v axi_dmac: Move transfer abort logic to data mover 2018-07-03 13:44:34 +02:00
src_fifo_inf.v axi_dmac: Move transfer abort logic to data mover 2018-07-03 13:44:34 +02:00