237 lines
7.2 KiB
Verilog
237 lines
7.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module src_axi_mm #(
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parameter ID_WIDTH = 3,
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parameter DMA_DATA_WIDTH = 64,
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parameter DMA_ADDR_WIDTH = 32,
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parameter BYTES_PER_BEAT_WIDTH = 3,
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parameter BEATS_PER_BURST_WIDTH = 4,
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parameter AXI_LENGTH_WIDTH = 8
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) (
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input m_axi_aclk,
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input m_axi_aresetn,
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input req_valid,
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output req_ready,
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input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address,
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input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
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input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes,
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input enable,
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output reg enabled = 1'b0,
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output bl_valid,
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input bl_ready,
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output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,
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/*
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output response_valid,
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input response_ready,
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output [1:0] response_resp,
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*/
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input [ID_WIDTH-1:0] request_id,
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output [ID_WIDTH-1:0] response_id,
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output [ID_WIDTH-1:0] data_id,
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output [ID_WIDTH-1:0] address_id,
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input address_eot,
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output fifo_valid,
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output [DMA_DATA_WIDTH-1:0] fifo_data,
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output [BYTES_PER_BEAT_WIDTH-1:0] fifo_valid_bytes,
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output fifo_last,
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// Read address
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input m_axi_arready,
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output m_axi_arvalid,
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output [DMA_ADDR_WIDTH-1:0] m_axi_araddr,
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output [AXI_LENGTH_WIDTH-1:0] m_axi_arlen,
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output [ 2:0] m_axi_arsize,
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output [ 1:0] m_axi_arburst,
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output [ 2:0] m_axi_arprot,
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output [ 3:0] m_axi_arcache,
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// Read data and response
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input [DMA_DATA_WIDTH-1:0] m_axi_rdata,
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output m_axi_rready,
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input m_axi_rvalid,
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input m_axi_rlast,
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input [ 1:0] m_axi_rresp
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);
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`include "inc_id.vh"
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reg [ID_WIDTH-1:0] id = 'h00;
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wire address_enabled;
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wire req_ready_ag;
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wire req_valid_ag;
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wire bl_ready_ag;
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wire bl_valid_ag;
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assign data_id = id;
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assign response_id = id;
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assign measured_last_burst_length = req_last_burst_length;
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reg [BYTES_PER_BEAT_WIDTH-1:0] last_beat_bytes;
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reg [BYTES_PER_BEAT_WIDTH-1:0] last_beat_bytes_mem[0:2**ID_WIDTH-1];
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assign fifo_valid_bytes = last_beat_bytes_mem[data_id];
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always @(posedge m_axi_aclk) begin
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if (bl_ready_ag == 1'b1 && bl_valid_ag == 1'b1) begin
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last_beat_bytes <= req_last_beat_bytes;
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end
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end
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always @(posedge m_axi_aclk) begin
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last_beat_bytes_mem[address_id] <= address_eot ? last_beat_bytes :
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{BYTES_PER_BEAT_WIDTH{1'b1}};
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end
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splitter #(
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.NUM_M(3)
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) i_req_splitter (
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.clk(m_axi_aclk),
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.resetn(m_axi_aresetn),
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.s_valid(req_valid),
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.s_ready(req_ready),
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.m_valid({
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bl_valid,
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bl_valid_ag,
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req_valid_ag}),
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.m_ready({
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bl_ready,
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bl_ready_ag,
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req_ready_ag}));
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address_generator #(
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.ID_WIDTH(ID_WIDTH),
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.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
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.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
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.DMA_DATA_WIDTH(DMA_DATA_WIDTH),
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.LENGTH_WIDTH(AXI_LENGTH_WIDTH),
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.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH)
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) i_addr_gen (
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.clk(m_axi_aclk),
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.resetn(m_axi_aresetn),
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.enable(enable),
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.enabled(address_enabled),
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.request_id(request_id),
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.id(address_id),
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.req_valid(req_valid_ag),
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.req_ready(req_ready_ag),
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.req_address(req_address),
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.bl_valid(bl_valid_ag),
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.bl_ready(bl_ready_ag),
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.measured_last_burst_length(req_last_burst_length),
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.eot(address_eot),
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.addr_ready(m_axi_arready),
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.addr_valid(m_axi_arvalid),
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.addr(m_axi_araddr),
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.len(m_axi_arlen),
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.size(m_axi_arsize),
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.burst(m_axi_arburst),
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.prot(m_axi_arprot),
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.cache(m_axi_arcache));
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assign fifo_valid = m_axi_rvalid;
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assign fifo_data = m_axi_rdata;
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assign fifo_last = m_axi_rlast;
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/*
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* There is a requirement that data_id <= address_id (modulo 2**ID_WIDTH). We
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* know that we will never receive data before we have requested it so there is
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* an implicit dependency between data_id and address_id and no need to
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* explicitly track it.
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*/
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always @(posedge m_axi_aclk) begin
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if (m_axi_aresetn == 1'b0) begin
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id <= 'h00;
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end else if (m_axi_rvalid == 1'b1 && m_axi_rlast == 1'b1) begin
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id <= inc_id(id);
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end
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end
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/*
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* We won't be receiving data before we've requested it and we won't request
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* data unless there is room in the store-and-forward memory.
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*/
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assign m_axi_rready = 1'b1;
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/*
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* We need to complete all bursts for which an address has been put onto the
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* AXI-MM interface.
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*/
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always @(posedge m_axi_aclk) begin
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if (m_axi_aresetn == 1'b0) begin
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enabled <= 1'b0;
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end else if (address_enabled == 1'b1) begin
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enabled <= 1'b1;
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end else if (id == address_id) begin
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enabled <= 1'b0;
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end
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end
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/* TODO
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`include "resp.vh"
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assign response_valid = 1'b0;
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assign response_resp = RESP_OKAY;
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reg [1:0] rresp;
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always @(posedge m_axi_aclk)
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begin
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if (m_axi_rvalid && m_axi_rready) begin
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if (m_axi_rresp != 2'b0)
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rresp <= m_axi_rresp;
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end
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end
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*/
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endmodule
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