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Bogdan Luncan 294b681196 ad9081: Proper reset sequence for versal transceivers 
- Removes the reset_tx_pll_and_datapath_in reset
- Connects gtreset_in to make use of the master reset found inside
the Transceiver Bridge IP
- Connects the necessary signals for the master reset between the
Transceiver Wizard and Transceiver Bridge

ad9209/vck190/system_top: Connect versal transceiver reset

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 		2023-05-16 12:13:55 +03:00
..
vck190 ad9081: Proper reset sequence for versal transceivers 2023-05-16 12:13:55 +03:00
Makefile ad9209: Initial vck190 design 2023-05-10 12:59:58 +03:00
Readme.md ad9209: Initial vck190 design 2023-05-10 12:59:58 +03:00

Readme.md

AD9209 HDL Project

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