Adrian Costina cd0701513a axi_logic_analyzer: Added an additional delay to the trigger, to be similar with the analog path		2017-03-14 18:00:42 +02:00
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Makefile	axi_logic_analyzer: Initial commit	2017-01-31 16:23:56 +02:00
axi_logic_analyzer.v	axi_logic_analyzer: Triggering changes on valid data	2017-03-14 15:25:00 +02:00
axi_logic_analyzer_constr.xdc	axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching	2017-02-27 14:19:54 +02:00
axi_logic_analyzer_ip.tcl	axi_logic_analyzer: Initial commit	2017-01-31 16:23:56 +02:00
axi_logic_analyzer_reg.v	axi_logic_analyzer: Initial commit	2017-01-31 16:23:56 +02:00
axi_logic_analyzer_trigger.v	axi_logic_analyzer: Added an additional delay to the trigger, to be similar with the analog path	2017-03-14 18:00:42 +02:00