177 lines
7.4 KiB
VHDL
177 lines
7.4 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- WISHBONE SPDIF IP Core ----
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---- ----
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---- This file is part of the SPDIF project ----
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---- http://www.opencores.org/cores/spdif_interface/ ----
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---- ----
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---- Description ----
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---- SPDIF receiver channel status capture module ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2004/07/19 16:58:37 gedra
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-- Fixed bug.
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--
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-- Revision 1.3 2004/06/27 16:16:55 gedra
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-- Signal renaming and bug fix.
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--
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-- Revision 1.2 2004/06/26 14:14:47 gedra
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-- Converted to numeric_std and fixed a few bugs.
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--
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-- Revision 1.1 2004/06/05 17:16:46 gedra
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-- Channel status/user data capture register
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--
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rx_package.all;
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entity rx_cap_reg is
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port (
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clk: in std_logic; -- clock
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rst: in std_logic; -- reset
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--cap_ctrl_wr: in std_logic; -- control register write
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--cap_ctrl_rd: in std_logic; -- control register read
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--cap_data_rd: in std_logic; -- data register read
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cap_reg: in std_logic_vector(31 downto 0);
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cap_din: in std_logic_vector(31 downto 0); -- write data
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rx_block_start: in std_logic; -- start of block signal
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ch_data: in std_logic; -- channel status/user data
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ud_a_en: in std_logic; -- user data ch. A enable
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ud_b_en: in std_logic; -- user data ch. B enable
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cs_a_en: in std_logic; -- channel status ch. A enable
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cs_b_en: in std_logic; -- channel status ch. B enable
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cap_dout: out std_logic_vector(31 downto 0); -- read data
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cap_evt: out std_logic); -- capture event (interrupt)
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end rx_cap_reg;
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architecture rtl of rx_cap_reg is
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signal cap_ctrl_bits, cap_ctrl_dout: std_logic_vector(31 downto 0);
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signal cap_reg_1, cap_new : std_logic_vector(31 downto 0);
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signal bitlen, cap_len : integer range 0 to 63;
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signal bitpos, cur_pos : integer range 0 to 255;
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signal chid, cdata, compared : std_logic;
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signal d_enable : std_logic_vector(3 downto 0);
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begin
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-- Data bus or'ing
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cap_dout <= cap_reg_1;-- when cap_data_rd = '1' else cap_ctrl_dout;
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chid <= cap_reg(6);
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cdata <= cap_reg(7);
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-- capture data register
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CDAT: process (clk, rst)
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begin
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if rst = '1' then
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cap_reg_1 <= (others => '0'); --
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cap_new <= (others => '0');
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cur_pos <= 0;
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cap_len <= 0;
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cap_evt <= '0';
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compared <= '0';
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bitpos <= 0;
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bitlen <= 0;
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else
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if rising_edge(clk) then
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bitlen <= to_integer(unsigned(cap_reg(5 downto 0)));
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bitpos <= to_integer(unsigned(cap_reg(15 downto 8)));
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if bitlen > 0 then -- bitlen = 0 disables the capture function
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-- bit counter, 0 to 191
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if rx_block_start = '1' then
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cur_pos <= 0;
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cap_len <= 0;
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cap_new <= (others => '0');
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compared <= '0';
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elsif cs_b_en = '1' then -- ch. status #2 comes last, count then
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cur_pos <= cur_pos + 1;
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end if;
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-- capture bits
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if cur_pos >= bitpos and cap_len < bitlen then
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case d_enable is
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when "0001" => -- user data channel A
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if cdata = '0' and chid = '0' then
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cap_new(cap_len) <= ch_data;
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cap_len <= cap_len + 1;
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end if;
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when "0010" => -- user data channel B
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if cdata = '0' and chid = '1' then
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cap_new(cap_len) <= ch_data;
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cap_len <= cap_len + 1;
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end if;
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when "0100" => -- channel status ch. A
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if cdata = '1' and chid = '0' then
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cap_new(cap_len) <= ch_data;
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cap_len <= cap_len + 1;
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end if;
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when "1000" => -- channel status ch. B
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if cdata = '1' and chid = '1' then
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cap_new(cap_len) <= ch_data;
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cap_len <= cap_len + 1;
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end if;
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when others => null;
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end case;
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end if;
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-- if all bits captured, check with previous data
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if cap_len = bitlen and compared = '0' then
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compared <= '1';
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-- event generated if captured bits differ
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if cap_reg_1 /= cap_new then
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cap_evt <= '1';
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end if;
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cap_reg_1 <= cap_new;
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else
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cap_evt <= '0';
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end if;
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end if;
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end if;
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end if;
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end process CDAT;
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d_enable(0) <= ud_a_en;
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d_enable(1) <= ud_b_en;
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d_enable(2) <= cs_a_en;
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d_enable(3) <= cs_b_en;
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end rtl;
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