| .. |
|
intel
|
library:axi_adrv9001: Initial version
|
2020-08-24 17:49:12 +03:00 |
|
Makefile
|
makefile: Regenerate make files
|
2020-10-20 12:51:10 +03:00 |
|
adrv9001_aligner4.v
|
library:axi_adrv9001: Initial version
|
2020-08-24 17:49:12 +03:00 |
|
adrv9001_aligner8.v
|
library:axi_adrv9001: Initial version
|
2020-08-24 17:49:12 +03:00 |
|
adrv9001_pack.v
|
library:axi_adrv9001: Initial version
|
2020-08-24 17:49:12 +03:00 |
|
adrv9001_rx.v
|
axi_adrv9001: Use global clocks for divided down clock
|
2021-01-26 15:22:41 +02:00 |
|
adrv9001_rx_link.v
|
library:axi_adrv9001: Initial version
|
2020-08-24 17:49:12 +03:00 |
|
adrv9001_tx.v
|
axi_adrv9001: Use global clocks for divided down clock
|
2021-01-26 15:22:41 +02:00 |
|
adrv9001_tx_link.v
|
library:axi_adrv9001: Initial version
|
2020-08-24 17:49:12 +03:00 |
|
axi_adrv9001.v
|
axi_adrv9001: Add opt-in synthesis parameters
|
2021-01-26 15:22:41 +02:00 |
|
axi_adrv9001_constr.sdc
|
library:axi_adrv9001: Initial version
|
2020-08-24 17:49:12 +03:00 |
|
axi_adrv9001_constr.xdc
|
library:axi_adrv9001: Initial version
|
2020-08-24 17:49:12 +03:00 |
|
axi_adrv9001_core.v
|
axi_adrv9001: Add opt-in synthesis parameters
|
2021-01-26 15:22:41 +02:00 |
|
axi_adrv9001_hw.tcl
|
axi_adrv9001: Quartus 19.3 updates
|
2021-03-04 11:13:10 +02:00 |
|
axi_adrv9001_if.v
|
library:axi_adrv9001: Initial version
|
2020-08-24 17:49:12 +03:00 |
|
axi_adrv9001_ip.tcl
|
axi_adrv9001: Add TDD support
|
2021-01-20 13:00:01 +02:00 |
|
axi_adrv9001_rx.v
|
axi_adrv9001: Add opt-in synthesis parameters
|
2021-01-26 15:22:41 +02:00 |
|
axi_adrv9001_rx_channel.v
|
axi_adrv9001:axi_adrv9001_rx_channel: fix ramp signal checking
|
2021-01-26 15:22:41 +02:00 |
|
axi_adrv9001_tdd.v
|
axi_adrv9001: Add TDD support
|
2021-01-20 13:00:01 +02:00 |
|
axi_adrv9001_tx.v
|
axi_adrv9001: Fix channel 3 for Tx1 in DMA mode
|
2021-03-04 11:13:10 +02:00 |
|
axi_adrv9001_tx_channel.v
|
library:axi_adrv9001: Initial version
|
2020-08-24 17:49:12 +03:00 |
50c4c3e815