118 lines
4.6 KiB
Verilog
118 lines
4.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module fmcadc2_spi (
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input spi_adf4355,
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input spi_adf4355_ce,
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input spi_clk,
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input [ 2:0] spi_csn,
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input spi_mosi,
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output spi_miso,
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output spi_adc_csn,
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output spi_adc_clk,
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inout spi_adc_sdio,
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output spi_adf4355_data_or_csn_0,
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output spi_adf4355_clk_or_csn_1,
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output spi_adf4355_le_or_clk,
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inout spi_adf4355_ce_or_sdio);
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// internal registers
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reg [ 5:0] spi_count = 'd0;
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reg spi_rd_wr_n = 'd0;
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reg spi_enable = 'd0;
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// internal signals
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wire spi_csn_s;
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wire spi_enable_s;
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// check on rising edge and change on falling edge
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assign spi_csn_s = & spi_csn;
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assign spi_enable_s = spi_enable & ~spi_csn_s;
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always @(posedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_count <= 6'd0;
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spi_rd_wr_n <= 1'd0;
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end else begin
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spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
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if (spi_count == 6'd0) begin
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spi_rd_wr_n <= spi_mosi;
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end
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end
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end
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always @(negedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_enable <= 1'b0;
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end else begin
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if (spi_count == 6'd16) begin
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spi_enable <= spi_rd_wr_n;
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end
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end
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end
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assign spi_miso = ((spi_adc_sdio & ~spi_csn[0]) | (~spi_adf4355 &
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spi_adf4355_ce_or_sdio & ~(spi_csn[1] & spi_csn[2])));
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// adc interface (3 wire)
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assign spi_adc_csn = spi_csn[0];
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assign spi_adc_clk = spi_clk;
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assign spi_adc_sdio = (spi_enable_s == 1'b0) ? spi_mosi : 1'bz;
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// adf4355 or normal (AMP/EXT)
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assign spi_adf4355_data_or_csn_0 = (spi_adf4355 == 1'b1) ? spi_mosi : spi_csn[1];
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assign spi_adf4355_clk_or_csn_1 = (spi_adf4355 == 1'b1) ? spi_clk : spi_csn[2];
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assign spi_adf4355_le_or_clk = (spi_adf4355 == 1'b1) ? spi_csn[1] : spi_clk;
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assign spi_adf4355_ce_or_sdio = (spi_adf4355 == 1'b1) ? spi_adf4355_ce :
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((spi_enable_s == 1'b0) ? spi_mosi : 1'bz);
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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