99 lines
3.1 KiB
Verilog
99 lines
3.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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// This is the LVDS/DDR interface
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`timescale 1ns/100ps
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module axi_ad9234_if (
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk,
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input [127:0] rx_data,
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// adc data output
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output adc_clk,
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input adc_rst,
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output [63:0] adc_data_a,
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output [63:0] adc_data_b,
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output adc_or_a,
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output adc_or_b,
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output reg adc_status);
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// internal registers
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// internal signals
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wire [15:0] adc_data_a_s3_s;
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wire [15:0] adc_data_a_s2_s;
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wire [15:0] adc_data_a_s1_s;
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wire [15:0] adc_data_a_s0_s;
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wire [15:0] adc_data_b_s3_s;
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wire [15:0] adc_data_b_s2_s;
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wire [15:0] adc_data_b_s1_s;
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wire [15:0] adc_data_b_s0_s;
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// adc clock is the reference clock
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assign adc_clk = rx_clk;
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assign adc_or_a = 1'b0;
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assign adc_or_b = 1'b0;
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// adc channels
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assign adc_data_a = { adc_data_a_s3_s, adc_data_a_s2_s,
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adc_data_a_s1_s, adc_data_a_s0_s};
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assign adc_data_b = { adc_data_b_s3_s, adc_data_b_s2_s,
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adc_data_b_s1_s, adc_data_b_s0_s};
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// data multiplex
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assign adc_data_a_s3_s = {rx_data[ 31: 24], rx_data[ 63: 56]};
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assign adc_data_a_s2_s = {rx_data[ 23: 16], rx_data[ 55: 48]};
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assign adc_data_a_s1_s = {rx_data[ 15: 8], rx_data[ 47: 40]};
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assign adc_data_a_s0_s = {rx_data[ 7: 0], rx_data[ 39: 32]};
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assign adc_data_b_s3_s = {rx_data[ 95: 88], rx_data[127:120]};
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assign adc_data_b_s2_s = {rx_data[ 87: 80], rx_data[119:112]};
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assign adc_data_b_s1_s = {rx_data[ 79: 72], rx_data[111:104]};
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assign adc_data_b_s0_s = {rx_data[ 71: 64], rx_data[103: 96]};
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// status
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always @(posedge rx_clk) begin
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if (adc_rst == 1'b1) begin
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adc_status <= 1'b0;
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end else begin
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adc_status <= 1'b1;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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