84 lines
2.5 KiB
Verilog
84 lines
2.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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module dmac_request_generator (
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input req_aclk,
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input req_aresetn,
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output [ID_WIDTH-1:0] request_id,
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input [ID_WIDTH-1:0] response_id,
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input req_valid,
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output reg req_ready,
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input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count,
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input enable,
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input pause,
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output eot
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);
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parameter ID_WIDTH = 3;
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parameter BURSTS_PER_TRANSFER_WIDTH = 17;
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`include "inc_id.h"
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/*
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* Here we only need to count the number of bursts, which means we can ignore
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* the lower bits of the byte count. The last last burst may not contain the
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* maximum number of bytes, but the address_generator and data_mover will take
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* care that only the requested ammount of bytes is transfered.
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*/
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reg [BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00;
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reg [ID_WIDTH-1:0] id;
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wire [ID_WIDTH-1:0] id_next = inc_id(id);
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assign eot = burst_count == 'h00;
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assign request_id = id;
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always @(posedge req_aclk)
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begin
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if (req_aresetn == 1'b0) begin
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burst_count <= 'h00;
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id <= 'h0;
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req_ready <= 1'b1;
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end else if (enable == 1'b0) begin
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req_ready <= 1'b1;
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end else begin
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if (req_ready) begin
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if (req_valid && enable) begin
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burst_count <= req_burst_count;
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req_ready <= 1'b0;
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end
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end else if (response_id != id_next && ~pause) begin
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if (eot)
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req_ready <= 1'b1;
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burst_count <= burst_count - 1'b1;
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id <= id_next;
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end
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end
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end
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endmodule
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