118 lines
3.1 KiB
VHDL
118 lines
3.1 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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--
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-- Each core or library found in this collection may have its own licensing terms.
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-- The user should keep this in in mind while exploring these cores.
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--
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-- Redistribution and use in source and binary forms,
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-- with or without modification of this file, are permitted under the terms of either
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-- (at the option of the user):
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--
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-- 1. The GNU General Public License version 2 as published by the
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-- Free Software Foundation, which can be found in the top level directory, or at:
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-- https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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--
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-- OR
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--
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-- 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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-- https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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--
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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entity fifo_synchronizer is
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generic (
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DEPTH : integer := 4;
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WIDTH : integer := 2
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);
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port (
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in_clk : in std_logic;
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in_resetn : in std_logic;
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in_data : in std_logic_vector(WIDTH - 1 downto 0);
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in_tick : in std_logic;
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out_clk : in std_logic;
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out_resetn : in std_logic;
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out_data : out std_logic_vector(WIDTH - 1 downto 0);
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out_tick : out std_logic
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);
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end fifo_synchronizer;
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architecture impl of fifo_synchronizer is
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type DATA_SYNC_FIFO_TYPE is array (0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
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signal fifo: DATA_SYNC_FIFO_TYPE;
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signal rd_addr : natural range 0 to DEPTH - 1;
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signal wr_addr : natural range 0 to DEPTH - 1;
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signal cdc_sync_stage0_tick : std_logic;
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signal cdc_sync_stage1_tick : std_logic;
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signal cdc_sync_stage2_tick : std_logic;
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signal cdc_sync_stage3_tick : std_logic;
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signal tick : std_logic;
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begin
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process (in_clk)
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begin
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if rising_edge(in_clk) then
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if in_tick = '1' then
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cdc_sync_stage0_tick <= not cdc_sync_stage0_tick;
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fifo(wr_addr) <= in_data;
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end if;
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end if;
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end process;
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process (in_clk)
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begin
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if rising_edge(in_clk) then
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if in_resetn = '0' then
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wr_addr <= 0;
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else
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if in_tick = '1' then
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wr_addr <= (wr_addr + 1) mod DEPTH;
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end if;
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end if;
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end if;
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end process;
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process (out_clk)
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begin
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if rising_edge(out_clk) then
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cdc_sync_stage1_tick <= cdc_sync_stage0_tick;
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cdc_sync_stage2_tick <= cdc_sync_stage1_tick;
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cdc_sync_stage3_tick <= cdc_sync_stage2_tick;
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end if;
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end process;
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tick <= cdc_sync_stage2_tick xor cdc_sync_stage3_tick;
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out_tick <= tick;
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process (out_clk)
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begin
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if rising_edge(out_clk) then
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if tick = '1' then
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out_data <= fifo(rd_addr);
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end if;
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end if;
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end process;
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process (out_clk)
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begin
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if rising_edge(out_clk) then
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if out_resetn = '0' then
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rd_addr <= 0;
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else
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if tick = '1' then
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rd_addr <= (rd_addr + 1) mod DEPTH;
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end if;
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end if;
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end if;
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end process;
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end;
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