Adrian Costina 89f7aadfb1 fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output ... This will allow for the transceivers to be reset by the axi_jesd_xcvr core		2016-02-23 11:31:07 +02:00
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a5gt	fmcjesdadc1: Fixed project	2016-02-19 14:09:57 +02:00
a5soc	Makefiles: Removed " from path	2015-11-27 14:02:46 +02:00
common	fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output	2016-02-23 11:31:07 +02:00
kc705	fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR	2016-02-09 12:00:27 +02:00
vc707	fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR	2016-02-09 12:30:56 +02:00
zc706	fmcjesdadc1: Added clock constraint for the ADC path	2016-01-22 15:46:20 +02:00
Makefile	Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries	2015-11-10 09:32:50 +02:00