462 lines
13 KiB
Verilog
462 lines
13 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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uart_sin,
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uart_sout,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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ddr3_ras_n,
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ddr3_reset_n,
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ddr3_we_n,
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sgmii_rxp,
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sgmii_rxn,
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sgmii_txp,
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sgmii_txn,
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phy_rstn,
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mgt_clk_p,
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mgt_clk_n,
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mdio_mdc,
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mdio_mdio,
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fan_pwm,
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linear_flash_addr,
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linear_flash_adv_ldn,
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linear_flash_ce_n,
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linear_flash_oen,
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linear_flash_wen,
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linear_flash_dq_io,
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gpio_lcd,
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gpio_bd,
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iic_rstn,
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iic_scl,
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iic_sda,
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rx_ref_clk_0_p,
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rx_ref_clk_0_n,
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rx_data_0_p,
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rx_data_0_n,
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rx_ref_clk_1_p,
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rx_ref_clk_1_n,
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rx_data_1_p,
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rx_data_1_n,
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rx_sysref_p,
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rx_sysref_n,
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rx_sync_0_p,
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rx_sync_0_n,
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rx_sync_1_p,
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rx_sync_1_n,
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spi_csn_0,
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spi_csn_1,
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spi_clk,
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spi_sdio,
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spi_dirn,
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trig_p,
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trig_n,
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vdither_p,
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vdither_n,
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pwr_good,
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dac_clk,
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dac_data,
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dac_sync_0,
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dac_sync_1,
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fd_1,
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irq_1,
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fd_0,
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irq_0,
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pwdn_1,
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rst_1,
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drst_1,
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arst_1,
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pwdn_0,
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rst_0,
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drst_0,
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arst_0);
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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input uart_sin;
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output uart_sout;
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output [ 13:0] ddr3_addr;
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output [ 2:0] ddr3_ba;
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output ddr3_cas_n;
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output [ 0:0] ddr3_ck_n;
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output [ 0:0] ddr3_ck_p;
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output [ 0:0] ddr3_cke;
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output [ 0:0] ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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inout [ 63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 7:0] ddr3_dqs_p;
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output [ 0:0] ddr3_odt;
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output ddr3_ras_n;
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output ddr3_reset_n;
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output ddr3_we_n;
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input sgmii_rxp;
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input sgmii_rxn;
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output sgmii_txp;
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output sgmii_txn;
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output phy_rstn;
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input mgt_clk_p;
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input mgt_clk_n;
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output mdio_mdc;
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inout mdio_mdio;
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output fan_pwm;
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output [26:1] linear_flash_addr;
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output linear_flash_adv_ldn;
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output linear_flash_ce_n;
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output linear_flash_oen;
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output linear_flash_wen;
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inout [15:0] linear_flash_dq_io;
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inout [ 6:0] gpio_lcd;
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inout [ 20:0] gpio_bd;
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output iic_rstn;
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inout iic_scl;
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inout iic_sda;
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input rx_ref_clk_0_p;
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input rx_ref_clk_0_n;
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input [ 7:0] rx_data_0_p;
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input [ 7:0] rx_data_0_n;
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input rx_ref_clk_1_p;
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input rx_ref_clk_1_n;
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input [ 7:0] rx_data_1_p;
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input [ 7:0] rx_data_1_n;
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output rx_sysref_p;
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output rx_sysref_n;
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output rx_sync_0_p;
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output rx_sync_0_n;
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output rx_sync_1_p;
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output rx_sync_1_n;
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output spi_csn_0;
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output spi_csn_1;
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output spi_clk;
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inout spi_sdio;
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output spi_dirn;
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output dac_clk;
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output dac_data;
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output dac_sync_0;
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output dac_sync_1;
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input trig_p;
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input trig_n;
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output vdither_p;
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output vdither_n;
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inout pwr_good;
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inout fd_1;
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inout irq_1;
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inout fd_0;
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inout irq_0;
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inout pwdn_1;
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inout rst_1;
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inout drst_1;
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inout arst_1;
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inout pwdn_0;
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inout rst_0;
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inout drst_0;
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inout arst_0;
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// internal registers
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reg adc_wr = 'd0;
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reg [511:0] adc_wdata = 'd0;
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// internal signals
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire [ 63:0] gpio_t;
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wire [ 7:0] spi_csn;
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wire spi_clk;
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wire spi_mosi;
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wire spi_miso;
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wire rx_ref_clk_0;
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wire rx_ref_clk_1;
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wire rx_sysref;
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wire rx_sync_0;
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wire rx_sync_1;
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wire adc_clk;
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wire adc_valid_0;
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wire adc_enable_0;
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wire [255:0] adc_data_0;
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wire adc_valid_1;
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wire adc_enable_1;
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wire [255:0] adc_data_1;
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// interleaving
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always @(posedge adc_clk) begin
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adc_wr <= adc_enable_0 & adc_enable_1;
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adc_wdata[((16*31)+15):(16*31)] <= adc_data_1[((16*15)+15):(16*15)];
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adc_wdata[((16*30)+15):(16*30)] <= adc_data_0[((16*15)+15):(16*15)];
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adc_wdata[((16*29)+15):(16*29)] <= adc_data_1[((16*14)+15):(16*14)];
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adc_wdata[((16*28)+15):(16*28)] <= adc_data_0[((16*14)+15):(16*14)];
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adc_wdata[((16*27)+15):(16*27)] <= adc_data_1[((16*13)+15):(16*13)];
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adc_wdata[((16*26)+15):(16*26)] <= adc_data_0[((16*13)+15):(16*13)];
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adc_wdata[((16*25)+15):(16*25)] <= adc_data_1[((16*12)+15):(16*12)];
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adc_wdata[((16*24)+15):(16*24)] <= adc_data_0[((16*12)+15):(16*12)];
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adc_wdata[((16*23)+15):(16*23)] <= adc_data_1[((16*11)+15):(16*11)];
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adc_wdata[((16*22)+15):(16*22)] <= adc_data_0[((16*11)+15):(16*11)];
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adc_wdata[((16*21)+15):(16*21)] <= adc_data_1[((16*10)+15):(16*10)];
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adc_wdata[((16*20)+15):(16*20)] <= adc_data_0[((16*10)+15):(16*10)];
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adc_wdata[((16*19)+15):(16*19)] <= adc_data_1[((16* 9)+15):(16* 9)];
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adc_wdata[((16*18)+15):(16*18)] <= adc_data_0[((16* 9)+15):(16* 9)];
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adc_wdata[((16*17)+15):(16*17)] <= adc_data_1[((16* 8)+15):(16* 8)];
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adc_wdata[((16*16)+15):(16*16)] <= adc_data_0[((16* 8)+15):(16* 8)];
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adc_wdata[((16*15)+15):(16*15)] <= adc_data_1[((16* 7)+15):(16* 7)];
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adc_wdata[((16*14)+15):(16*14)] <= adc_data_0[((16* 7)+15):(16* 7)];
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adc_wdata[((16*13)+15):(16*13)] <= adc_data_1[((16* 6)+15):(16* 6)];
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adc_wdata[((16*12)+15):(16*12)] <= adc_data_0[((16* 6)+15):(16* 6)];
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adc_wdata[((16*11)+15):(16*11)] <= adc_data_1[((16* 5)+15):(16* 5)];
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adc_wdata[((16*10)+15):(16*10)] <= adc_data_0[((16* 5)+15):(16* 5)];
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adc_wdata[((16* 9)+15):(16* 9)] <= adc_data_1[((16* 4)+15):(16* 4)];
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adc_wdata[((16* 8)+15):(16* 8)] <= adc_data_0[((16* 4)+15):(16* 4)];
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adc_wdata[((16* 7)+15):(16* 7)] <= adc_data_1[((16* 3)+15):(16* 3)];
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adc_wdata[((16* 6)+15):(16* 6)] <= adc_data_0[((16* 3)+15):(16* 3)];
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adc_wdata[((16* 5)+15):(16* 5)] <= adc_data_1[((16* 2)+15):(16* 2)];
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adc_wdata[((16* 4)+15):(16* 4)] <= adc_data_0[((16* 2)+15):(16* 2)];
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adc_wdata[((16* 3)+15):(16* 3)] <= adc_data_1[((16* 1)+15):(16* 1)];
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adc_wdata[((16* 2)+15):(16* 2)] <= adc_data_0[((16* 1)+15):(16* 1)];
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adc_wdata[((16* 1)+15):(16* 1)] <= adc_data_1[((16* 0)+15):(16* 0)];
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adc_wdata[((16* 0)+15):(16* 0)] <= adc_data_0[((16* 0)+15):(16* 0)];
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end
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// spi
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assign iic_rstn = 1'b1;
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assign fan_pwm = 1'b1;
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assign dac_clk = spi_clk;
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assign dac_data = spi_mosi;
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assign dac_sync_1 = spi_csn[3];
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assign dac_sync_0 = spi_csn[2];
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assign spi_csn_1 = spi_csn[1];
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assign spi_csn_0 = spi_csn[0];
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// instantiations
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IBUFDS_GTE2 i_ibufds_rx_ref_clk_0 (
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.CEB (1'd0),
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.I (rx_ref_clk_0_p),
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.IB (rx_ref_clk_0_n),
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.O (rx_ref_clk_0),
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.ODIV2 ());
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IBUFDS_GTE2 i_ibufds_rx_ref_clk_1 (
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.CEB (1'd0),
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.I (rx_ref_clk_1_p),
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.IB (rx_ref_clk_1_n),
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.O (rx_ref_clk_1),
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.ODIV2 ());
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OBUFDS i_obufds_rx_sysref (
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.I (rx_sysref),
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.O (rx_sysref_p),
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.OB (rx_sysref_n));
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OBUFDS i_obufds_rx_sync_0 (
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.I (rx_sync_0),
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.O (rx_sync_0_p),
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.OB (rx_sync_0_n));
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OBUFDS i_obufds_rx_sync_1 (
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.I (rx_sync_1),
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.O (rx_sync_1_p),
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.OB (rx_sync_1_n));
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IBUFDS i_ibufds_trig (
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.I (trig_p),
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.IB (trig_n),
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.O (gpio_i[46]));
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OBUFDS i_obufds_vdither (
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.I (gpio_o[45]),
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.O (vdither_p),
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.OB (vdither_n));
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fmcadc5_spi i_fmcadc5_spi (
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.spi_csn_0 (spi_csn_0),
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.spi_csn_1 (spi_csn_1),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio),
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.spi_dirn (spi_dirn));
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ad_iobuf #(.DATA_WIDTH(13)) i_iobuf (
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.dt (gpio_t[44:32]),
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.di (gpio_o[44:32]),
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.do (gpio_i[44:32]),
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.dio ({ pwr_good, // 44
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fd_1, // 43
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irq_1, // 42
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fd_0, // 41
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irq_0, // 40
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pwdn_1, // 39
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rst_1, // 38
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drst_1, // 37
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arst_1, // 36
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pwdn_0, // 35
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rst_0, // 34
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drst_0, // 33
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arst_0})); // 32
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ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
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.dt (gpio_t[20:0]),
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.di (gpio_o[20:0]),
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.do (gpio_i[20:0]),
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.dio (gpio_bd));
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system_wrapper i_system_wrapper (
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.adc_clk (adc_clk),
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.adc_data_0 (adc_data_0),
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.adc_data_1 (adc_data_1),
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.adc_enable_0 (adc_enable_0),
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.adc_enable_1 (adc_enable_1),
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.adc_valid_0 (adc_valid_0),
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.adc_valid_1 (adc_valid_1),
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.adc_wdata (adc_wdata),
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.adc_wr (adc_wr),
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_cs_n (ddr3_cs_n),
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.ddr3_dm (ddr3_dm),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.ddr3_odt (ddr3_odt),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.gpio0_i (gpio_i[31:0]),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio1_i (gpio_i[63:32]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.gpio_lcd_tri_io (gpio_lcd),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.linear_flash_addr (linear_flash_addr),
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.linear_flash_adv_ldn (linear_flash_adv_ldn),
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.linear_flash_ce_n (linear_flash_ce_n),
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.linear_flash_dq_io(linear_flash_dq_io),
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.linear_flash_oen (linear_flash_oen),
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.linear_flash_wen (linear_flash_wen),
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.mb_intr_06 (1'b0),
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.mb_intr_07 (1'b0),
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.mb_intr_08 (1'b0),
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.mb_intr_12 (1'b0),
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.mb_intr_14 (1'b0),
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.mb_intr_15 (1'b0),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.mgt_clk_clk_n (mgt_clk_n),
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.mgt_clk_clk_p (mgt_clk_p),
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.phy_rstn (phy_rstn),
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.phy_sd (1'b1),
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.rx_data_0_n (rx_data_0_n),
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.rx_data_0_p (rx_data_0_p),
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.rx_data_1_n (rx_data_1_n),
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.rx_data_1_p (rx_data_1_p),
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.rx_ref_clk_0 (rx_ref_clk_0),
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.rx_ref_clk_1 (rx_ref_clk_1),
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|
.rx_sync_0 (rx_sync_0),
|
|
.rx_sync_1 (rx_sync_1),
|
|
.rx_sysref (rx_sysref),
|
|
.sgmii_rxn (sgmii_rxn),
|
|
.sgmii_rxp (sgmii_rxp),
|
|
.sgmii_txn (sgmii_txn),
|
|
.sgmii_txp (sgmii_txp),
|
|
.spi_clk_i (1'b0),
|
|
.spi_clk_o (spi_clk),
|
|
.spi_csn_i (8'hff),
|
|
.spi_csn_o (spi_csn),
|
|
.spi_sdi_i (spi_miso),
|
|
.spi_sdo_i (1'b0),
|
|
.spi_sdo_o (spi_mosi),
|
|
.sys_clk_n (sys_clk_n),
|
|
.sys_clk_p (sys_clk_p),
|
|
.sys_rst (sys_rst),
|
|
.uart_sin (uart_sin),
|
|
.uart_sout (uart_sout));
|
|
|
|
endmodule
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|
|
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// ***************************************************************************
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// ***************************************************************************
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