104 lines
3.2 KiB
Systemverilog
104 lines
3.2 KiB
Systemverilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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package axi_tdd_pkg;
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typedef enum logic [1:0] {
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IDLE = 2'b00,
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ARMED = 2'b01,
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WAITING = 2'b10,
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RUNNING = 2'b11} state_t;
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localparam
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PCORE_VERSION = 32'h00020061,
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PCORE_MAGIC = 32'h5444444E; // "TDDN", big endian
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// register address offset
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localparam
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ADDR_TDD_VERSION = 8'h00,
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ADDR_TDD_ID = 8'h01,
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ADDR_TDD_SCRATCH = 8'h02,
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ADDR_TDD_IDENTIFICATION = 8'h03,
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ADDR_TDD_INTERFACE = 8'h04,
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ADDR_TDD_DEF_POLARITY = 8'h05,
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ADDR_TDD_CONTROL = 8'h10,
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ADDR_TDD_CH_ENABLE = 8'h11,
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ADDR_TDD_CH_POLARITY = 8'h12,
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ADDR_TDD_BURST_COUNT = 8'h13,
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ADDR_TDD_STARTUP_DELAY = 8'h14,
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ADDR_TDD_FRAME_LENGTH = 8'h15,
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ADDR_TDD_SYNC_CNT_LOW = 8'h16,
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ADDR_TDD_SYNC_CNT_HIGH = 8'h17,
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ADDR_TDD_STATUS = 8'h18,
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ADDR_TDD_CH_ON = 8'h20,
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ADDR_TDD_CH_OFF = 8'h21;
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// channel offset values
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localparam
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CH0 = 0,
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CH1 = 1,
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CH2 = 2,
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CH3 = 3,
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CH4 = 4,
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CH5 = 5,
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CH6 = 6,
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CH7 = 7,
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CH8 = 8,
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CH9 = 9,
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CH10 = 10,
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CH11 = 11,
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CH12 = 12,
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CH13 = 13,
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CH14 = 14,
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CH15 = 15,
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CH16 = 16,
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CH17 = 17,
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CH18 = 18,
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CH19 = 19,
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CH20 = 20,
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CH21 = 21,
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CH22 = 22,
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CH23 = 23,
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CH24 = 24,
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CH25 = 25,
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CH26 = 26,
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CH27 = 27,
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CH28 = 28,
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CH29 = 29,
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CH30 = 30,
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CH31 = 31;
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endpackage
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