106 lines
3.7 KiB
Tcl
106 lines
3.7 KiB
Tcl
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package require qsys
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package require quartus::device
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_intel.tcl
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set_module_property NAME axi_ad9144
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set_module_property DESCRIPTION "AXI AD9144 Interface"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_ad9144
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set_module_property ELABORATION_CALLBACK p_axi_ad9144
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set_module_property VALIDATION_CALLBACK info_param_validate
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# files
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ad_ip_files axi_ad9144 [list \
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$ad_hdl_dir/library/intel/common/ad_mul.v \
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$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
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$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
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$ad_hdl_dir/library/common/ad_dds_sine.v \
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$ad_hdl_dir/library/common/ad_dds_2.v \
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$ad_hdl_dir/library/common/ad_dds_1.v \
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$ad_hdl_dir/library/common/ad_dds.v \
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$ad_hdl_dir/library/common/ad_perfect_shuffle.v \
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$ad_hdl_dir/library/common/ad_rst.v \
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$ad_hdl_dir/library/common/up_axi.v \
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$ad_hdl_dir/library/common/up_xfer_cntrl.v \
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$ad_hdl_dir/library/common/up_xfer_status.v \
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$ad_hdl_dir/library/common/up_clock_mon.v \
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$ad_hdl_dir/library/common/up_dac_common.v \
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$ad_hdl_dir/library/common/up_dac_channel.v \
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\
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v \
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v \
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v \
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v \
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v \
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v \
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v \
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\
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axi_ad9144.v \
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$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
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$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
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$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
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$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
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]
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# parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DEFAULT_VALUE 0
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set_parameter_property ID DISPLAY_NAME ID
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set_parameter_property ID TYPE INTEGER
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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add_parameter QUAD_OR_DUAL_N INTEGER 0
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set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 0
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set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N
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set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER
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set_parameter_property QUAD_OR_DUAL_N UNITS None
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set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
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adi_add_auto_fpga_spec_params
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# axi4 slave
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
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# transceiver interface
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ad_interface clock tx_clk input 1
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add_interface if_tx_data avalon_streaming source
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add_interface_port if_tx_data tx_data data output 128*(QUAD_OR_DUAL_N+1)
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add_interface_port if_tx_data tx_valid valid output 1
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add_interface_port if_tx_data tx_ready ready input 1
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set_interface_property if_tx_data associatedClock if_tx_clk
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set_interface_property if_tx_data dataBitsPerSymbol 128
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# dma interface
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ad_interface clock dac_clk output 1
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for {set i 0} {$i < 4} {incr i} {
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add_interface dac_ch_${i} conduit end
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add_interface_port dac_ch_${i} dac_enable_${i} enable Output 1
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add_interface_port dac_ch_${i} dac_valid_${i} valid Output 1
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add_interface_port dac_ch_${i} dac_ddata_${i} data Input 64
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set_interface_property dac_ch_${i} associatedClock if_tx_clk
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set_interface_property dac_ch_${i} associatedReset none
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}
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ad_interface signal dac_dunf input 1 unf
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proc p_axi_ad9144 {} {
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if {[get_parameter_value QUAD_OR_DUAL_N] != 1} {
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set_interface_property dac_ch_2 ENABLED false
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set_interface_property dac_ch_3 ENABLED false
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}
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}
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