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Lars-Peter Clausen 2e173201d4 daq2: daq2_qsys.tcl: Use sys_dma_clk 
Use the sys_dma_clk clock module for clock and reset signals of the data
path, rather than using the A10GX specific sys_ddr3_cntrl signals. This
enables compatibility for all Altera/Intel platforms.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-07-17 17:38:20 +02:00
..
a10gx hdlmake.pl- updates 2017-06-06 16:10:05 -04:00
common daq2: daq2_qsys.tcl: Use sys_dma_clk 2017-07-17 17:38:20 +02:00
kc705 Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
kcu105 Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
vc707 Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
zc706 Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
zcu102 Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
Makefile
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