cd0c981b50
In case of axi_interconnects, when just one slave and master interface is active, the 'Interconnect Optimization Strategy' is disabled. So this parameter should be set just if there is more than one slave interface. |
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README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects
Branches
Each release has its own branch and master always synced with the latest release. To find out more information about the latest release please check the release notes. Every branch, which has dev in its name, is a development branch and should handle it accordingly.