221 lines
6.8 KiB
Verilog
221 lines
6.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ADC channel-
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`timescale 1ns/100ps
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module axi_ad9652_channel (
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// adc interface
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adc_clk,
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adc_rst,
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adc_data,
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adc_or,
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// channel interface
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adc_dcfilter_data_out,
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adc_dcfilter_data_in,
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adc_iqcor_data,
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adc_enable,
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up_adc_pn_err,
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up_adc_pn_oos,
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up_adc_or,
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// processor interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack);
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// parameters
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parameter IQSEL = 0;
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parameter CHID = 0;
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parameter DP_DISABLE = 0;
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// adc interface
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input adc_clk;
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input adc_rst;
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input [15:0] adc_data;
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input adc_or;
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// channel interface
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output [15:0] adc_dcfilter_data_out;
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input [15:0] adc_dcfilter_data_in;
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output [15:0] adc_iqcor_data;
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output adc_enable;
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output up_adc_pn_err;
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output up_adc_pn_oos;
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output up_adc_or;
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// processor interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_rack;
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// internal signals
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wire [15:0] adc_dcfilter_data_i_s;
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wire [15:0] adc_dcfilter_data_q_s;
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wire adc_iqcor_enb_s;
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wire adc_dcfilt_enb_s;
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wire [15:0] adc_dcfilt_offset_s;
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wire [15:0] adc_dcfilt_coeff_s;
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wire [15:0] adc_iqcor_coeff_1_s;
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wire [15:0] adc_iqcor_coeff_2_s;
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wire [ 3:0] adc_pnseq_sel_s;
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wire adc_pn_err_s;
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wire adc_pn_oos_s;
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// iq correction inputs
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assign adc_dcfilter_data_i_s = (IQSEL == 1) ? adc_dcfilter_data_in : adc_dcfilter_data_out;
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assign adc_dcfilter_data_q_s = (IQSEL == 1) ? adc_dcfilter_data_out : adc_dcfilter_data_in;
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axi_ad9652_pnmon i_pnmon (
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.adc_clk (adc_clk),
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.adc_data (adc_data),
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.adc_pn_oos (adc_pn_oos_s),
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.adc_pn_err (adc_pn_err_s),
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.adc_pnseq_sel (adc_pnseq_sel_s));
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generate
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if (DP_DISABLE == 1) begin
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assign adc_dcfilter_data_out = adc_data;
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end else begin
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ad_dcfilter i_ad_dcfilter (
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.clk (adc_clk),
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.valid (1'b1),
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.data (adc_data),
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.valid_out (),
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.data_out (adc_dcfilter_data_out),
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.dcfilt_enb (adc_dcfilt_enb_s),
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.dcfilt_coeff (adc_dcfilt_coeff_s),
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.dcfilt_offset (adc_dcfilt_offset_s));
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end
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endgenerate
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generate
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if (DP_DISABLE == 1) begin
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assign adc_iqcor_data = (IQSEL == 1) ? adc_dcfilter_data_q_s : adc_dcfilter_data_i_s;
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end else begin
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ad_iqcor #(.IQSEL(IQSEL)) i_ad_iqcor (
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.clk (adc_clk),
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.valid (1'b1),
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.data_i (adc_dcfilter_data_i_s),
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.data_q (adc_dcfilter_data_q_s),
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.valid_out (),
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.data_out (adc_iqcor_data),
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.iqcor_enable (adc_iqcor_enb_s),
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.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
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.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
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end
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endgenerate
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up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_enable (adc_enable),
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.adc_iqcor_enb (adc_iqcor_enb_s),
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.adc_dcfilt_enb (adc_dcfilt_enb_s),
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.adc_dfmt_se (),
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.adc_dfmt_type (),
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.adc_dfmt_enable (),
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.adc_dcfilt_offset (adc_dcfilt_offset_s),
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.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
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.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
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.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
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.adc_pnseq_sel (adc_pnseq_sel_s),
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.adc_data_sel (),
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.adc_pn_err (adc_pn_err_s),
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.adc_pn_oos (adc_pn_oos_s),
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.adc_or (adc_or),
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.up_adc_pn_err (up_adc_pn_err),
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.up_adc_pn_oos (up_adc_pn_oos),
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.up_adc_or (up_adc_or),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_decimation_m (),
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.up_usr_decimation_n (),
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.adc_usr_datatype_be (1'b0),
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.adc_usr_datatype_signed (1'b1),
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.adc_usr_datatype_shift (8'd0),
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.adc_usr_datatype_total_bits (8'd16),
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.adc_usr_datatype_bits (8'd16),
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.adc_usr_decimation_m (16'd1),
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.adc_usr_decimation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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