Laszlo Nagy cdaaa49a2a axi_ad9361: sync dac_valid to adc_valid ... Sync the two valid signals to keep a fixed phase relationship between the Rx ant Tx channels, this way avoiding +/- 1 sample differences on the Tx-Rx latency between consecutive transfers.		2019-09-27 17:52:10 +03:00
..
intel	axi_ad9361/intel: Rename varibles with alt_* pre-fix	2019-06-29 06:53:51 +03:00
xilinx	cosmetics: Change Altera to Intel in comments	2019-06-29 06:53:51 +03:00
Makefile	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
axi_ad9361.v	axi_ad9361: sync dac_valid to adc_valid	2019-09-27 17:52:10 +03:00
axi_ad9361_constr.sdc	library/axi_ad9361: tdd false paths	2016-05-04 13:42:12 -04:00
axi_ad9361_constr.xdc	axi_ad9361: Update constraint file	2017-08-04 16:20:33 +01:00
axi_ad9361_delay.tcl	move/rename - delay script belongs to ad9361	2017-03-10 12:44:32 -05:00
axi_ad9361_hw.tcl	scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface	2019-06-29 06:53:51 +03:00
axi_ad9361_ip.tcl	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00
axi_ad9361_rx.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
axi_ad9361_rx_channel.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
axi_ad9361_rx_pnmon.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
axi_ad9361_tdd.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
axi_ad9361_tdd_if.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
axi_ad9361_tx.v	axi_ad9361: sync dac_valid to adc_valid	2019-09-27 17:52:10 +03:00
axi_ad9361_tx_channel.v	axi_ad9361: Updates for ad_dds phase acc wrapper	2018-07-18 18:19:30 +03:00