145 lines
4.6 KiB
Verilog
145 lines
4.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_clock_mon #(
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parameter TOTAL_WIDTH = 32
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) (
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// processor interface
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input up_rstn,
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input up_clk,
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output reg [TOTAL_WIDTH-1:0] up_d_count,
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// device interface
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input d_rst,
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input d_clk
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);
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// internal registers
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reg [15:0] up_count = 'd1;
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reg up_count_run = 'd0;
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reg up_count_running_m1 = 'd0;
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reg up_count_running_m2 = 'd0;
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reg up_count_running_m3 = 'd0;
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reg d_count_run_m1 = 'd0;
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reg d_count_run_m2 = 'd0;
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reg d_count_run_m3 = 'd0;
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reg [TOTAL_WIDTH:0] d_count = 'd0;
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// internal signals
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wire up_count_capture_s;
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wire d_count_reset_s;
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// processor reference
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// Capture on the falling edge of running
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assign up_count_capture_s = up_count_running_m3 == 1'b1 && up_count_running_m2 == 1'b0;
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_count_running_m1 <= 1'b0;
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up_count_running_m2 <= 1'b0;
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up_count_running_m3 <= 1'b0;
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end else begin
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up_count_running_m1 <= d_count_run_m3;
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up_count_running_m2 <= up_count_running_m1;
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up_count_running_m3 <= up_count_running_m2;
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end
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end
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_d_count <= 'd0;
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up_count_run <= 1'b0;
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end else begin
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if (up_count_running_m3 == 1'b0) begin
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up_count_run <= 1'b1;
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end else if (up_count == 'h00) begin
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up_count_run <= 1'b0;
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end
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if (up_count_capture_s == 1'b1) begin
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up_d_count <= d_count[TOTAL_WIDTH-1:0];
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end else if (up_count == 'h00 && up_count_run != up_count_running_m3) begin
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up_d_count <= 'h00;
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end
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end
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end
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always @(posedge up_clk) begin
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if (up_count_run == 1'b0 && up_count_running_m3 == 1'b0) begin
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up_count <= 'h01;
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end else begin
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up_count <= up_count + 1'b1;
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end
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end
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// device free running
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// Reset on the rising edge of run
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assign d_count_reset_s = d_count_run_m3 == 1'b0 && d_count_run_m2 == 1'b1;
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always @(posedge d_clk or posedge d_rst) begin
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if (d_rst == 1'b1) begin
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d_count_run_m1 <= 1'b0;
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d_count_run_m2 <= 1'b0;
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d_count_run_m3 <= 1'b0;
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end else begin
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d_count_run_m1 <= up_count_run;
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d_count_run_m2 <= d_count_run_m1;
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d_count_run_m3 <= d_count_run_m2;
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end
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end
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always @(posedge d_clk) begin
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if (d_count_reset_s == 1'b1) begin
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d_count <= 'h00;
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end else if (d_count_run_m3 == 1'b1) begin
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if (d_count[TOTAL_WIDTH] == 1'b0) begin
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d_count <= d_count + 1'b1;
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end else begin
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d_count <= {TOTAL_WIDTH+1{1'b1}};
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end
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end
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end
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endmodule
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