pluto_hdl_adi/library
Adrian Costina ce4f9bf906 up_dac_common: rename internal signals 2017-05-15 18:58:26 +03:00
..
altera altera- infer latest versions 2017-05-12 13:40:14 -04:00
axi_ad5766 axi_ad5766: Add missing ports to up_dac_common instance 2017-05-11 17:25:31 +03:00
axi_ad6676 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_ad7616 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ad9122 altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_ad9144 altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_ad9152 altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_ad9162 axi dac cores: Add missing ports to up_dac_common instance 2017-05-12 13:37:34 +03:00
axi_ad9234 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_ad9250 altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_ad9265 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_ad9361 altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_ad9371 altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_ad9434 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_ad9467 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_ad9625 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_ad9643 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_ad9652 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_ad9671 altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_ad9680 altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_ad9684 altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_ad9739a axi dac cores: Add missing ports to up_dac_common instance 2017-05-12 13:37:34 +03:00
axi_ad9963 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_adc_decimate hdlmake updates 2017-04-25 15:46:26 -04:00
axi_adc_trigger axi_adc_trigger: Reduce AXI address width 2017-04-18 12:17:41 +02:00
axi_clkgen axi_clkgen: Propagate clock settings to output pins 2017-04-20 20:36:33 +02:00
axi_dac_interpolate hdlmake updates 2017-04-25 15:46:26 -04:00
axi_dmac altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_fmcadc5_sync fmcadc5-sync: added a convenience timer 2017-05-11 12:39:39 -04:00
axi_generic_adc axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_gpreg all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_hdmi_rx all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_hdmi_tx altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_i2s_adi library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase 2017-04-18 12:17:41 +02:00
axi_intr_monitor updated makefiles 2016-12-09 23:06:41 +02:00
axi_logic_analyzer axi_logic_analyzer: Reduce AXI address width 2017-04-18 12:17:40 +02:00
axi_mc_controller library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
axi_mc_current_monitor axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_mc_speed axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
axi_rd_wr_combiner hdlmake updates 2017-04-25 15:46:26 -04:00
axi_spdif_rx library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase 2017-04-18 12:17:41 +02:00
axi_spdif_tx library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase 2017-04-18 12:17:41 +02:00
axi_usb_fx3 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
cn0363 updated makefiles 2016-12-09 23:06:41 +02:00
common up_dac_common: rename internal signals 2017-05-15 18:58:26 +03:00
cordic_demod updated makefiles 2016-12-09 23:06:41 +02:00
interfaces interfaces- remove channel based pll reset 2016-11-22 11:34:29 -05:00
prcfg all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
scripts version check- change to critical warning 2017-05-12 09:51:48 -04:00
spi_engine spi_engine_offload: Add a CDC module for trigger reception 2017-05-04 12:14:06 +03:00
util_adcfifo altera- default to latest version 2017-05-12 13:25:17 -04:00
util_axis_fifo library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase 2017-04-18 12:17:41 +02:00
util_axis_resize updated makefiles 2016-12-09 23:06:41 +02:00
util_bsplit altera- default to latest version 2017-05-12 13:25:17 -04:00
util_ccat all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_cic hdlmake updates 2017-04-25 15:46:26 -04:00
util_clkdiv hdlmake: Fix util_clkdiv Makefile issue. sort library master Makefile 2017-04-26 09:58:17 +03:00
util_cpack altera- default to latest version 2017-05-12 13:25:17 -04:00
util_dacfifo altera- default to latest version 2017-05-12 13:25:17 -04:00
util_extract all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_fir_dec util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero 2017-03-09 16:33:17 +02:00
util_fir_int util_fir_int: Shifted data so that the amplitude at the output of the filter is the same with the input 2017-03-08 14:29:26 +02:00
util_gmii_to_rgmii all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_i2c_mixer updated makefiles 2016-12-09 23:06:41 +02:00
util_mfifo hdlmake updates 2017-04-25 15:46:26 -04:00
util_pmod_adc all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_pmod_fmeter all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_pulse_gen util_pulse_gen: Add Makefile 2017-04-27 11:28:25 +03:00
util_rfifo altera- default to latest version 2017-05-12 13:25:17 -04:00
util_sigma_delta_spi updated makefiles 2016-12-09 23:06:41 +02:00
util_tdd_sync all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_upack altera- default to latest version 2017-05-12 13:25:17 -04:00
util_var_fifo hdlmake updates 2017-04-25 15:46:26 -04:00
util_wfifo altera- default to latest version 2017-05-12 13:25:17 -04:00
xilinx altera- default to latest version 2017-05-12 13:25:17 -04:00
Makefile hdlmake.pl updates 2017-05-04 13:59:47 -04:00