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Lars-Peter Clausen ce8bcfd192 fmcjesdadc1: Remove wire that is a redeclaration of a port 
Fixes the following warning:
	[Synth 8-2611] redeclaration of ansi port rx_sysref is not allowed

This is a leftover of commit 1c23cf4621 ("all: Update verilog files to
verilog-2001").

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2018-02-16 13:32:26 +01:00
library axi_clkgen: add ultrascale series support 2018-02-13 17:33:38 +02:00
projects fmcjesdadc1: Remove wire that is a redeclaration of a port 2018-02-16 13:32:26 +01:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore 2016-12-19 15:37:05 +00:00
LICENSE license: GPL must be GPL v2 2017-05-31 18:18:45 +03:00
LICENSE_ADIBSD license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_GPL2 license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_LGPL license: Add top level license files 2017-05-29 09:57:39 +03:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

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