cycollineau b93c1e6e90 intel/adi_jesd204: add bonded clock network support (#408) ... * jesd204b: add bonding clocks feature (fix for some routing issues) * intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6 * intel/adi_jesd204: clock network option renamed according to intel documentation * intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>		2020-01-09 17:45:32 +02:00
..
Makefile	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
jesd204_phy_glue.v	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
jesd204_phy_glue_hw.tcl	intel/adi_jesd204: add bonded clock network support (#408)	2020-01-09 17:45:32 +02:00
jesd204_phy_hw.tcl	intel/adi_jesd204: add bonded clock network support (#408)	2020-01-09 17:45:32 +02:00