7eba8326dd
There is no guarantee that the external reset de-assertion is synchronous to the sys_clk, yet the clock bridge marks the reset de-assertion as synchronized to the clock. This can cause recovery or removal timing violations for the registers affected by this reset signal and potentially bring the system into an invalid state after the reset is de-asserted. Mark the reset as not synchronized to the clock signal, this will make sure that Qsys inserts the proper reset synchronizers where required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| a10soc_plddr4_assign.tcl | ||
| a10soc_plddr4_dacfifo_qsys.tcl | ||
| a10soc_system_assign.tcl | ||
| a10soc_system_qsys.tcl | ||