zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
1,711 Commits
1 Branch
0 Tags
23 MiB
Verilog 61.7%
Tcl 31.2%
Makefile 3.5%
VHDL 1.9%
SystemVerilog 1%
Other 0.6%
 
 
 
 
 
 
Go to file
Istvan Csomortani cfc4046821 fmcomms2: Add a synchronization interface for TDD mode. 
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write  0x01 into TDD register 0x50.
 		2015-07-29 14:10:56 +03:00
library fmcomms2: Add a synchronization interface for TDD mode. 2015-07-29 14:10:56 +03:00
projects fmcomms2: Add a synchronization interface for TDD mode. 2015-07-29 14:10:56 +03:00
.gitattributes Add .gitattributes file 2015-07-01 18:43:51 +02:00
.gitignore gitignore: add non-project stuff 2015-05-01 13:17:14 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md Update README.md 2015-05-20 17:38:08 +03:00

README.md

#HDL Reference Designs

Analog Devices HDL libraries and projects

##NOTE

Beware! This branch is just a realease candidate. Final release expected at end of June.

###Tools version:

###Documentation and support

For first time users, it is highly recommended to go through our HDL user guide.

For support please visit our FPGA Reference Designs Support Community on EngineerZone.