319 lines
12 KiB
Verilog
Executable File
319 lines
12 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_cpack (
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// adc interface
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adc_rst,
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adc_clk,
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adc_enable_0,
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adc_valid_0,
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adc_data_0,
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adc_enable_1,
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adc_valid_1,
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adc_data_1,
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adc_enable_2,
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adc_valid_2,
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adc_data_2,
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adc_enable_3,
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adc_valid_3,
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adc_data_3,
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adc_enable_4,
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adc_valid_4,
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adc_data_4,
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adc_enable_5,
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adc_valid_5,
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adc_data_5,
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adc_enable_6,
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adc_valid_6,
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adc_data_6,
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adc_enable_7,
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adc_valid_7,
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adc_data_7,
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// fifo interface
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adc_valid,
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adc_sync,
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adc_data);
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// parameters
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parameter CH_DW = 32;
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parameter CH_CNT = 8;
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localparam CH_SCNT = CH_DW/16;
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localparam CH_MCNT = 8;
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localparam P_DW = CH_CNT*CH_DW;
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localparam P_CNT = CH_CNT;
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localparam P_SCNT = P_DW/16;
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// adc interface
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input adc_rst;
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input adc_clk;
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input adc_enable_0;
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input adc_valid_0;
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input [(CH_DW-1):0] adc_data_0;
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input adc_enable_1;
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input adc_valid_1;
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input [(CH_DW-1):0] adc_data_1;
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input adc_enable_2;
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input adc_valid_2;
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input [(CH_DW-1):0] adc_data_2;
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input adc_enable_3;
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input adc_valid_3;
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input [(CH_DW-1):0] adc_data_3;
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input adc_enable_4;
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input adc_valid_4;
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input [(CH_DW-1):0] adc_data_4;
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input adc_enable_5;
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input adc_valid_5;
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input [(CH_DW-1):0] adc_data_5;
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input adc_enable_6;
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input adc_valid_6;
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input [(CH_DW-1):0] adc_data_6;
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input adc_enable_7;
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input adc_valid_7;
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input [(CH_DW-1):0] adc_data_7;
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// fifo interface
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output adc_valid;
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output adc_sync;
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output [((CH_CNT*CH_DW)-1):0] adc_data;
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// internal registers
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reg adc_valid_d = 'd0;
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reg [((CH_MCNT*CH_DW)-1):0] adc_data_d = 'd0;
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reg adc_mux_valid = 'd0;
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reg [(CH_MCNT-1):0] adc_mux_enable = 'd0;
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reg [((CH_SCNT*16*79)-1):0] adc_mux_data = 'd0;
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reg adc_valid = 'd0;
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reg adc_sync = 'd0;
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reg [((CH_CNT*CH_DW)-1):0] adc_data = 'd0;
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// internal signals
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wire [(CH_MCNT-1):0] adc_enable_s;
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wire [(CH_MCNT-1):0] adc_valid_s;
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wire [((CH_MCNT*CH_DW)-1):0] adc_data_s;
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wire [((CH_MCNT*CH_DW)-1):0] adc_data_intlv_s;
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wire [(CH_SCNT-1):0] adc_mux_valid_s;
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wire [(CH_SCNT-1):0] adc_mux_enable_0_s;
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wire [(CH_SCNT-1):0] adc_mux_enable_1_s;
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wire [(CH_SCNT-1):0] adc_mux_enable_2_s;
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wire [(CH_SCNT-1):0] adc_mux_enable_3_s;
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wire [(CH_SCNT-1):0] adc_mux_enable_4_s;
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wire [(CH_SCNT-1):0] adc_mux_enable_5_s;
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wire [(CH_SCNT-1):0] adc_mux_enable_6_s;
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wire [(CH_SCNT-1):0] adc_mux_enable_7_s;
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wire [((CH_SCNT*16*1)-1):0] adc_mux_data_0_s;
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wire [((CH_SCNT*16*2)-1):0] adc_mux_data_1_s;
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wire [((CH_SCNT*16*3)-1):0] adc_mux_data_2_s;
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wire [((CH_SCNT*16*4)-1):0] adc_mux_data_3_s;
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wire [((CH_SCNT*16*5)-1):0] adc_mux_data_4_s;
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wire [((CH_SCNT*16*6)-1):0] adc_mux_data_5_s;
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wire [((CH_SCNT*16*7)-1):0] adc_mux_data_6_s;
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wire [((CH_SCNT*16*8)-1):0] adc_mux_data_7_s;
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wire [(CH_MCNT-1):0] adc_dsf_valid_s;
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wire [(CH_MCNT-1):0] adc_dsf_sync_s;
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wire [(P_DW-1):0] adc_dsf_data_s[(CH_MCNT-1):0];
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// loop variables
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genvar n;
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// making things a bit easier
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assign adc_enable_s = { adc_enable_7, adc_enable_6, adc_enable_5, adc_enable_4,
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adc_enable_3, adc_enable_2, adc_enable_1, adc_enable_0};
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assign adc_valid_s = { adc_valid_7, adc_valid_6, adc_valid_5, adc_valid_4,
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adc_valid_3, adc_valid_2, adc_valid_1, adc_valid_0};
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assign adc_data_s = { adc_data_7, adc_data_6, adc_data_5, adc_data_4,
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adc_data_3, adc_data_2, adc_data_1, adc_data_0};
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// adc first channel must be always on (doesn't have to be enabled)
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always @(posedge adc_clk) begin
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if (adc_rst == 1'b1) begin
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adc_valid_d <= 'd0;
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end else begin
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adc_valid_d <= adc_valid_0;
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end
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end
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// mw requires unused to be zero
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generate
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for (n = 0; n < CH_MCNT; n = n + 1) begin: g_in
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always @(posedge adc_clk) begin
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if ((adc_rst == 1'b1) && (adc_enable_s[n] == 1'b0)) begin
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adc_data_d[((CH_DW*(n+1))-1):(CH_DW*n)] <= 'd0;
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end else if (adc_valid_s[n] == 1'b1) begin
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adc_data_d[((CH_DW*(n+1))-1):(CH_DW*n)] <=
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adc_data_s[((CH_DW*(n+1))-1):(CH_DW*n)];
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end
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end
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end
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endgenerate
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// interleave data
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generate
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for (n = 0; n < CH_SCNT; n = n + 1) begin: g_intlv
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assign adc_data_intlv_s[((16*CH_MCNT*(n+1))-1):(16*CH_MCNT*n)] =
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{ adc_data_d[(((CH_DW*7)+(16*(n+1)))-1):((CH_DW*7)+(16*n))],
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adc_data_d[(((CH_DW*6)+(16*(n+1)))-1):((CH_DW*6)+(16*n))],
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adc_data_d[(((CH_DW*5)+(16*(n+1)))-1):((CH_DW*5)+(16*n))],
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adc_data_d[(((CH_DW*4)+(16*(n+1)))-1):((CH_DW*4)+(16*n))],
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adc_data_d[(((CH_DW*3)+(16*(n+1)))-1):((CH_DW*3)+(16*n))],
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adc_data_d[(((CH_DW*2)+(16*(n+1)))-1):((CH_DW*2)+(16*n))],
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adc_data_d[(((CH_DW*1)+(16*(n+1)))-1):((CH_DW*1)+(16*n))],
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adc_data_d[(((CH_DW*0)+(16*(n+1)))-1):((CH_DW*0)+(16*n))]};
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end
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endgenerate
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// mux
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generate
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for (n = 0; n < CH_SCNT; n = n + 1) begin: g_mux
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util_cpack_mux i_mux (
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.adc_clk (adc_clk),
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.adc_valid (adc_valid_d),
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.adc_enable (adc_enable_s),
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.adc_data (adc_data_intlv_s[((16*CH_MCNT*(n+1))-1):(16*CH_MCNT*n)]),
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.adc_mux_valid (adc_mux_valid_s[n]),
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.adc_mux_enable_0 (adc_mux_enable_0_s[n]),
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.adc_mux_data_0 (adc_mux_data_0_s[(((n+1)*16*1)-1):(n*16*1)]),
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.adc_mux_enable_1 (adc_mux_enable_1_s[n]),
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.adc_mux_data_1 (adc_mux_data_1_s[(((n+1)*16*2)-1):(n*16*2)]),
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.adc_mux_enable_2 (adc_mux_enable_2_s[n]),
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.adc_mux_data_2 (adc_mux_data_2_s[(((n+1)*16*3)-1):(n*16*3)]),
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.adc_mux_enable_3 (adc_mux_enable_3_s[n]),
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.adc_mux_data_3 (adc_mux_data_3_s[(((n+1)*16*4)-1):(n*16*4)]),
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.adc_mux_enable_4 (adc_mux_enable_4_s[n]),
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.adc_mux_data_4 (adc_mux_data_4_s[(((n+1)*16*5)-1):(n*16*5)]),
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.adc_mux_enable_5 (adc_mux_enable_5_s[n]),
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.adc_mux_data_5 (adc_mux_data_5_s[(((n+1)*16*6)-1):(n*16*6)]),
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.adc_mux_enable_6 (adc_mux_enable_6_s[n]),
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.adc_mux_data_6 (adc_mux_data_6_s[(((n+1)*16*7)-1):(n*16*7)]),
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.adc_mux_enable_7 (adc_mux_enable_7_s[n]),
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.adc_mux_data_7 (adc_mux_data_7_s[(((n+1)*16*8)-1):(n*16*8)]));
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end
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endgenerate
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// concat
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always @(posedge adc_clk) begin
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adc_mux_valid <= & adc_mux_valid_s;
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adc_mux_enable[0] <= & adc_mux_enable_0_s;
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adc_mux_enable[1] <= & adc_mux_enable_1_s;
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adc_mux_enable[2] <= & adc_mux_enable_2_s;
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adc_mux_enable[3] <= & adc_mux_enable_3_s;
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adc_mux_enable[4] <= & adc_mux_enable_4_s;
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adc_mux_enable[5] <= & adc_mux_enable_5_s;
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adc_mux_enable[6] <= & adc_mux_enable_6_s;
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adc_mux_enable[7] <= & adc_mux_enable_7_s;
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adc_mux_data[((CH_SCNT*16* 9)-1):(CH_SCNT*16* 1)] <= 'd0;
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adc_mux_data[((CH_SCNT*16*19)-1):(CH_SCNT*16*12)] <= 'd0;
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adc_mux_data[((CH_SCNT*16*29)-1):(CH_SCNT*16*23)] <= 'd0;
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adc_mux_data[((CH_SCNT*16*39)-1):(CH_SCNT*16*34)] <= 'd0;
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adc_mux_data[((CH_SCNT*16*49)-1):(CH_SCNT*16*45)] <= 'd0;
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adc_mux_data[((CH_SCNT*16*59)-1):(CH_SCNT*16*56)] <= 'd0;
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adc_mux_data[((CH_SCNT*16*69)-1):(CH_SCNT*16*67)] <= 'd0;
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adc_mux_data[((CH_SCNT*16*79)-1):(CH_SCNT*16*78)] <= 'd0;
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adc_mux_data[((CH_SCNT*16* 1)-1):(CH_SCNT*16* 0)] <= adc_mux_data_0_s;
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adc_mux_data[((CH_SCNT*16*12)-1):(CH_SCNT*16*10)] <= adc_mux_data_1_s;
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adc_mux_data[((CH_SCNT*16*23)-1):(CH_SCNT*16*20)] <= adc_mux_data_2_s;
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adc_mux_data[((CH_SCNT*16*34)-1):(CH_SCNT*16*30)] <= adc_mux_data_3_s;
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adc_mux_data[((CH_SCNT*16*45)-1):(CH_SCNT*16*40)] <= adc_mux_data_4_s;
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adc_mux_data[((CH_SCNT*16*56)-1):(CH_SCNT*16*50)] <= adc_mux_data_5_s;
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adc_mux_data[((CH_SCNT*16*67)-1):(CH_SCNT*16*60)] <= adc_mux_data_6_s;
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adc_mux_data[((CH_SCNT*16*78)-1):(CH_SCNT*16*70)] <= adc_mux_data_7_s;
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end
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// store & fwd
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generate
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for (n = 0; n < P_CNT; n = n + 1) begin: g_dsf
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util_cpack_dsf #(
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.CH_MCNT (CH_MCNT),
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.P_CNT (P_CNT),
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.CH_DW (CH_DW),
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.CH_ICNT ((n+1)))
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i_dsf (
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.adc_clk (adc_clk),
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.adc_valid (adc_mux_valid),
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.adc_enable (adc_mux_enable[n]),
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.adc_data (adc_mux_data[((CH_SCNT*16*((11*n)+1))-1):(CH_SCNT*16*10*n)]),
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.adc_dsf_valid (adc_dsf_valid_s[n]),
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.adc_dsf_sync (adc_dsf_sync_s[n]),
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.adc_dsf_data (adc_dsf_data_s[n]));
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end
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endgenerate
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generate
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if (CH_MCNT > P_CNT) begin
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for (n = P_CNT; n < CH_MCNT; n = n + 1) begin: g_def
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assign adc_dsf_valid_s[n] = 'd0;
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assign adc_dsf_sync_s[n] = 'd0;
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assign adc_dsf_data_s[n] = 'd0;
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end
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end
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endgenerate
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always @(posedge adc_clk) begin
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adc_valid <= | adc_dsf_valid_s;
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adc_sync <= | adc_dsf_sync_s;
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adc_data <= adc_dsf_data_s[7] | adc_dsf_data_s[6] |
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adc_dsf_data_s[5] | adc_dsf_data_s[4] |
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adc_dsf_data_s[3] | adc_dsf_data_s[2] |
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adc_dsf_data_s[1] | adc_dsf_data_s[0];
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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