pluto_hdl_adi/library/jesd204/jesd204_tx
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
..
Makefile all: Rename altera to intel 2019-06-29 06:53:51 +03:00
jesd204_tx.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
jesd204_tx_constr.sdc jesd204: Add Altera/Intel IP support 2017-08-21 11:09:42 +02:00
jesd204_tx_constr.ttcl jesd204_rx/tx: make SYSREF IOB placement optional 2018-07-24 09:16:24 +03:00
jesd204_tx_ctrl.v sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
jesd204_tx_hw.tcl library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
jesd204_tx_ip.tcl library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
jesd204_tx_lane.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00