123 lines
4.0 KiB
Verilog
123 lines
4.0 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_tx_lane #(
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parameter DATA_PATH_WIDTH = 4
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) (
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input clk,
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input [DATA_PATH_WIDTH-1:0] eof,
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input eomf,
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input cgs_enable,
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input [DATA_PATH_WIDTH*8-1:0] ilas_data,
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input [DATA_PATH_WIDTH-1:0] ilas_charisk,
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input [DATA_PATH_WIDTH*8-1:0] tx_data,
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input tx_ready,
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output reg [DATA_PATH_WIDTH*8-1:0] phy_data,
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output reg [DATA_PATH_WIDTH-1:0] phy_charisk,
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input cfg_disable_scrambler
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);
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wire [DATA_PATH_WIDTH*8-1:0] scrambled_data;
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wire [7:0] scrambled_char[0:DATA_PATH_WIDTH-1];
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reg [7:0] char_align[0:DATA_PATH_WIDTH-1];
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jesd204_scrambler #(
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.WIDTH(DATA_PATH_WIDTH*8),
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.DESCRAMBLE(0)
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) i_scrambler (
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.clk(clk),
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.reset(~tx_ready),
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.enable(~cfg_disable_scrambler),
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.data_in(tx_data),
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.data_out(scrambled_data)
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);
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generate
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genvar i;
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for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
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assign scrambled_char[i] = scrambled_data[i*8+7:i*8];
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always @(*) begin
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if (i == DATA_PATH_WIDTH-1 && eomf == 1'b1) begin
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char_align[i] <= 8'h7c; // /A/
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end else begin
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char_align[i] <= 8'hfc; // /F/
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end
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end
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always @(posedge clk) begin
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if (cgs_enable == 1'b1) begin
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phy_charisk[i] <= 1'b1;
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end else if (eof[i] == 1'b1 && scrambled_char[i] == char_align[i]) begin
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phy_charisk[i] <= 1'b1;
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end else begin
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phy_charisk[i] <= ilas_charisk[i];
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end
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end
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end
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endgenerate
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always @(posedge clk) begin
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if (cgs_enable == 1'b1) begin
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phy_data <= {DATA_PATH_WIDTH{8'hbc}};
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end else begin
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case (tx_ready)
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1'b0: phy_data <= ilas_data;
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default: phy_data <= scrambled_data;
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endcase
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end
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end
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endmodule
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