zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library/axi_dmac
History
Laszlo Nagy cff06bd779 axi_dmac: Use AXI3 for DMAC in Intel projects 
The buffers inside the interconnect are sized based on maximum burst sizes
the masters can produce.
For AXI4 the max burst size is 128 but for these projects for the
default burst size of 128 bytes the DMACs are creating only burst of 8 or
16 beats depending on the bus width (128bits and 64 bits respectively).

These burst sizes can fit in the AXI3 protocol where the max burst
length is 16. Therefore the interconnect will be reduced.

The observed reduction is around 4 Mb of block RAM per project.
Another benefit is a better timing closure,
since these buffers reside in the DDR3 clock domain.
 		2018-08-21 14:08:14 +03:00
..
bd axi_dmac: fix address width detection 2018-07-20 18:12:24 +03:00
tb axi_dmac: Enforce transfer length and stride alignments 2018-07-03 13:44:34 +02:00
2d_transfer.v axi_dmac: TLAST support for 2d transfers 2018-07-13 13:46:40 +03:00
Makefile axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
address_generator.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
axi_dmac.v axi_dmac: diagnostic interface in bursts 2018-07-10 12:30:34 +03:00
axi_dmac_burst_memory.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
axi_dmac_constr.sdc axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_constr.ttcl axi_dmac: Remove unused constraint 2018-07-06 16:31:40 +03:00
axi_dmac_hw.tcl axi_dmac: Use AXI3 for DMAC in Intel projects 2018-08-21 14:08:14 +03:00
axi_dmac_ip.tcl axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
axi_dmac_pkg_sv.ttcl axi_dmac: ttcl file support for simulation 2018-07-11 11:30:22 +03:00
axi_dmac_regmap.v axi_dmac: Enforce transfer length and stride alignments 2018-07-03 13:44:34 +02:00
axi_dmac_regmap_request.v axi_dmac: Enforce transfer length and stride alignments 2018-07-03 13:44:34 +02:00
axi_dmac_reset_manager.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
axi_dmac_resize_dest.v axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_resize_src.v axi_dmac: Remove backpressure from the source pipeline 2018-07-03 13:44:34 +02:00
axi_dmac_transfer.v axi_dmac: TLAST support for 2d transfers 2018-07-13 13:46:40 +03:00
axi_register_slice.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
data_mover.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
dest_axi_mm.v axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
dest_axi_stream.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
dest_fifo_inf.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
inc_id.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_arb.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_generator.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
resp.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_generator.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_handler.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
splitter.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
src_axi_mm.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
src_axi_stream.v axi_dmac: Move transfer abort logic to data mover 2018-07-03 13:44:34 +02:00
src_fifo_inf.v axi_dmac: Move transfer abort logic to data mover 2018-07-03 13:44:34 +02:00