116 lines
4.1 KiB
Verilog
116 lines
4.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module fmcadc2_spi (
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input spi_adf4355,
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input spi_adf4355_ce,
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input spi_clk,
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input [ 2:0] spi_csn,
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input spi_mosi,
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output spi_miso,
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output spi_adc_csn,
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output spi_adc_clk,
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inout spi_adc_sdio,
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output spi_adf4355_data_or_csn_0,
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output spi_adf4355_clk_or_csn_1,
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output spi_adf4355_le_or_clk,
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inout spi_adf4355_ce_or_sdio);
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// internal registers
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reg [ 5:0] spi_count = 'd0;
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reg spi_rd_wr_n = 'd0;
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reg spi_enable = 'd0;
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// internal signals
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wire spi_csn_s;
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wire spi_enable_s;
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// check on rising edge and change on falling edge
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assign spi_csn_s = & spi_csn;
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assign spi_enable_s = spi_enable & ~spi_csn_s;
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always @(posedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_count <= 6'd0;
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spi_rd_wr_n <= 1'd0;
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end else begin
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spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
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if (spi_count == 6'd0) begin
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spi_rd_wr_n <= spi_mosi;
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end
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end
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end
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always @(negedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_enable <= 1'b0;
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end else begin
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if (spi_count == 6'd16) begin
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spi_enable <= spi_rd_wr_n;
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end
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end
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end
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assign spi_miso = ((spi_adc_sdio & ~spi_csn[0]) | (~spi_adf4355 &
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spi_adf4355_ce_or_sdio & ~(spi_csn[1] & spi_csn[2])));
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// adc interface (3 wire)
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assign spi_adc_csn = spi_csn[0];
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assign spi_adc_clk = spi_clk;
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assign spi_adc_sdio = (spi_enable_s == 1'b0) ? spi_mosi : 1'bz;
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// adf4355 or normal (AMP/EXT)
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assign spi_adf4355_data_or_csn_0 = (spi_adf4355 == 1'b1) ? spi_mosi : spi_csn[1];
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assign spi_adf4355_clk_or_csn_1 = (spi_adf4355 == 1'b1) ? spi_clk : spi_csn[2];
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assign spi_adf4355_le_or_clk = (spi_adf4355 == 1'b1) ? spi_csn[1] : spi_clk;
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assign spi_adf4355_ce_or_sdio = (spi_adf4355 == 1'b1) ? spi_adf4355_ce :
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((spi_enable_s == 1'b0) ? spi_mosi : 1'bz);
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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