zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
338 Commits
1 Branch
0 Tags
23 MiB
Verilog 61.7%
Tcl 31.2%
Makefile 3.5%
VHDL 1.9%
SystemVerilog 1%
Other 0.6%
 
 
 
 
 
 
Go to file
Adrian Costina d33fb07587 usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32. 
GPIOs for which the directions is known, have been specifically assigned.

The SPI clock has been changed to a lower frequency.
 		2014-09-16 15:56:19 -04:00
library axi_dmac: src_fifo_inf: Clear pipeline when no transfers are active 2014-09-16 21:02:05 +02:00
projects usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32. 2014-09-16 15:56:19 -04:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Add a link to EngineerZone 2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga