265 lines
8.2 KiB
Verilog
265 lines
8.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2016(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [31:0] gpio_bd,
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output hdmi_out_clk,
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output hdmi_vsync,
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output hdmi_hsync,
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output hdmi_data_e,
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output [15:0] hdmi_data,
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output spdif,
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output i2s_mclk,
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output i2s_bclk,
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output i2s_lrclk,
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output i2s_sdata_out,
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input i2s_sdata_in,
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inout iic_scl,
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inout iic_sda,
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inout [ 1:0] iic_mux_scl,
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inout [ 1:0] iic_mux_sda,
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input otg_vbusoc,
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inout ad7768_0_reset,
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inout ad7768_0_sync_out,
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inout ad7768_0_sync_in,
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inout [ 3:0] ad7768_0_gpio,
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inout ad7768_1_reset,
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inout ad7768_1_sync_out,
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inout ad7768_1_sync_in,
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inout [ 3:0] ad7768_1_gpio,
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input ad7768_0_mclk,
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input ad7768_1_mclk,
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output ad7768_mclk_return,
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input ad7768_0_spi_miso,
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output ad7768_0_spi_mosi,
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output ad7768_0_spi_sclk,
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output ad7768_0_spi_cs,
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input ad7768_0_drdy,
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input ad7768_1_spi_miso,
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output ad7768_1_spi_mosi,
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output ad7768_1_spi_sclk,
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output ad7768_1_spi_cs,
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input ad7768_1_drdy);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 1:0] iic_mux_scl_i_s;
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wire [ 1:0] iic_mux_scl_o_s;
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wire iic_mux_scl_t_s;
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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wire ad7768_0_mclk_s;
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wire ad7768_1_mclk_s;
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// instantiations
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ad_cmos_clk i_ad7768_0_mclk_receiver(
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.rst (1'b1),
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.locked (),
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.clk_in (ad7768_0_mclk),
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.clk(ad7768_0_mclk_s));
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ad_cmos_clk i_ad7768_1_mclk_receiver(
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.rst (1'b1),
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.locked (),
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.clk_in (ad7768_1_mclk),
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.clk(ad7768_1_mclk_s));
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assign ad7768_mclk_return = ad7768_0_mclk_s;
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ad_iobuf #(
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.DATA_WIDTH(7)
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) i_iobuf_ad7768_1_gpio (
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.dio_t(gpio_t[54:48]),
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.dio_i(gpio_o[54:48]),
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.dio_o(gpio_i[54:48]),
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.dio_p({ad7768_1_gpio,
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ad7768_1_sync_in,
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ad7768_1_sync_out,
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ad7768_1_reset}));
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ad_iobuf #(
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.DATA_WIDTH(7)
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) i_iobuf_ad7768_0_gpio (
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.dio_t(gpio_t[38:32]),
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.dio_i(gpio_o[38:32]),
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.dio_o(gpio_i[38:32]),
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.dio_p({ad7768_0_gpio,
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ad7768_0_sync_in,
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ad7768_0_sync_out,
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ad7768_0_reset}));
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ad_iobuf #(
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.DATA_WIDTH(32)
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) i_iobuf (
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.dio_t(gpio_t[31:0]),
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.dio_i(gpio_o[31:0]),
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.dio_o(gpio_i[31:0]),
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.dio_p(gpio_bd));
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iic_mux_scl (
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.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
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.dio_i(iic_mux_scl_o_s),
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.dio_o(iic_mux_scl_i_s),
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.dio_p(iic_mux_scl));
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iic_mux_sda (
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.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
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.dio_i(iic_mux_sda_o_s),
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.dio_o(iic_mux_sda_i_s),
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.dio_p(iic_mux_sda));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.i2s_bclk (i2s_bclk),
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.i2s_lrclk (i2s_lrclk),
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.i2s_mclk (i2s_mclk),
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.i2s_sdata_in (i2s_sdata_in),
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.i2s_sdata_out (i2s_sdata_out),
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.iic_fmc_scl_io (iic_scl),
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.iic_fmc_sda_io (iic_sda),
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.iic_mux_scl_i (iic_mux_scl_i_s),
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.iic_mux_scl_o (iic_mux_scl_o_s),
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.iic_mux_scl_t (iic_mux_scl_t_s),
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.iic_mux_sda_i (iic_mux_sda_i_s),
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.iic_mux_sda_o (iic_mux_sda_o_s),
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.iic_mux_sda_t (iic_mux_sda_t_s),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.otg_vbusoc (otg_vbusoc),
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.spdif (spdif),
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.adc1_spi_sdo (ad7768_0_spi_mosi),
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.adc1_spi_sdo_t (),
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.adc1_spi_sdi (ad7768_0_spi_miso),
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.adc1_spi_cs (ad7768_0_spi_cs),
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.adc1_spi_sclk (ad7768_0_spi_sclk),
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.adc1_data_ready (ad7768_0_drdy),
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.adc2_spi_sdo (ad7768_1_spi_mosi),
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.adc2_spi_sdo_t (),
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.adc2_spi_sdi (ad7768_1_spi_miso),
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.adc2_spi_cs (ad7768_1_spi_cs),
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.adc2_spi_sclk (ad7768_1_spi_sclk),
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.adc2_data_ready (ad7768_1_drdy));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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