120 lines
3.8 KiB
Verilog
120 lines
3.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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//`timescale 1n/100ps;
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module usdrx1_cpld (
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// Bank 1.8 V
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input [13:0] fmc_dac_db,
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input fmc_dac_sleep,
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input fmc_clkd_spi_sclk,
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input fmc_clkd_spi_csb,
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inout fmc_clkd_spi_sdio,
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input fmc_clkd_syncn,
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input fmc_clkd_resetn,
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//fmc_clkd_status,
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//tbd1
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//tbd2
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//tbd3
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// Bank 3.3 V
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output [13:0] dac_db,
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output dac_sleep,
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output clkd_spi_sclk,
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output clkd_spi_csb,
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inout clkd_spi_sdio,
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//clkd_status,
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output clkd_syncn,
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output clkd_resetn);
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reg [15:0] cnt ;
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reg fpga_to_clkd ; // 1 if fpga sends data to ad9517, 0 if fpga reads data from ad9517
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reg spi_r_wn ;
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assign dac_db = fmc_dac_db;
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assign dac_sleep = fmc_dac_sleep;
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assign clkd_spi_sclk = fmc_clkd_spi_sclk;
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assign clkd_spi_csb = fmc_clkd_spi_csb;
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assign clkd_spi_sdio = fpga_to_clkd ? fmc_clkd_spi_sdio : 1'bZ;
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assign fmc_clkd_spi_sdio = fpga_to_clkd ? 1'bZ :clkd_spi_sdio;
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assign clkd_syncn = fmc_clkd_syncn;
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assign clkd_resetn = fmc_clkd_resetn;
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//assign fmc_clkd_status = clkd_status;
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always @ (posedge fmc_clkd_spi_sclk or posedge fmc_clkd_spi_csb)
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begin
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if (fmc_clkd_spi_csb == 1'b1)
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begin
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cnt <= 0;
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spi_r_wn <= 1;
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end
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else
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begin
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cnt <= cnt + 1;
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if (cnt == 0)
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begin
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spi_r_wn <= fmc_clkd_spi_sdio;
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end
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end
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end
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always @(negedge fmc_clkd_spi_sclk or posedge fmc_clkd_spi_csb)
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begin
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if (fmc_clkd_spi_csb == 1'b1)
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begin
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fpga_to_clkd <= 1;
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end
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else
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begin
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if (cnt == 16)
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begin
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fpga_to_clkd <= ~spi_r_wn;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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