Jorge Marques 15250232f9 axi_dmac: Fix constraints coverage and empty to list warnings ... Due to nets being optimized at IP-level during the no-OOC synthesis flow, constraints related to req_clk (request clock) were not being applied, causing the design to not meet timing. The fix considers the synchronous modes, appending the possible resulting req_clk's names after the synthesis flow. Due to grounded signals in the DMA_TYPE_SRC != DMA_TYPE_STREAM_AXI config., sync_rewind is removed during synthesis, even so, constraints were trying to be applied to those nets. To resolve this, sync_rewind block was moved to inside the generate. Vivado seems to properly suppress "Empty list" warnings when the circuit does not exist because of a generate rule. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>		2023-07-10 12:28:59 +00:00
..
bd	axi_dmac: Add suport for 64 bit address width	2022-10-18 16:59:18 +03:00
tb	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
Makefile	library & projects: Update Makefiles	2023-01-27 11:54:05 +02:00
address_generator.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
axi_dmac.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
axi_dmac_burst_memory.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
axi_dmac_constr.sdc	axi_dmac: preparation work for reporting length of partial transfers	2018-09-07 11:38:04 +03:00
axi_dmac_constr.ttcl	axi_dmac: Fix constraints coverage and empty to list warnings	2023-07-10 12:28:59 +00:00
axi_dmac_hw.tcl	axi_dmac: Add suport for 64 bit address width	2022-10-18 16:59:18 +03:00
axi_dmac_ip.tcl	axi_dmac: Add suport for 64 bit address width	2022-10-18 16:59:18 +03:00
axi_dmac_pkg_sv.ttcl	axi_dmac: ttcl file support for simulation	2018-07-11 11:30:22 +03:00
axi_dmac_regmap.v	axi_dmac: Add suport for 64 bit address width	2022-10-18 16:59:18 +03:00
axi_dmac_regmap_request.v	axi_dmac: Add suport for 64 bit address width	2022-10-18 16:59:18 +03:00
axi_dmac_reset_manager.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
axi_dmac_resize_dest.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
axi_dmac_resize_src.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
axi_dmac_response_manager.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
axi_dmac_transfer.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
axi_register_slice.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
data_mover.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
dest_axi_mm.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
dest_axi_stream.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
dest_fifo_inf.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
dmac_2d_transfer.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
inc_id.vh	axi_dmac: renamed .h files to .vh	2018-07-11 11:30:22 +03:00
request_arb.v	axi_dmac: Fix constraints coverage and empty to list warnings	2023-07-10 12:28:59 +00:00
request_generator.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
resp.vh	axi_dmac: renamed .h files to .vh	2018-07-11 11:30:22 +03:00
response_generator.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
response_handler.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
splitter.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
src_axi_mm.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
src_axi_stream.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00
src_fifo_inf.v	libraries: Update modules according to guideline	2022-06-28 18:06:56 +03:00