64 lines
2.2 KiB
Tcl
64 lines
2.2 KiB
Tcl
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proc ad_tdd_gen_create {ip_name
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num_of_channels
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{default_polarity 0}
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{reg_counter_width 32}
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{burst_counter_width 32}
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{sync_counter_width 64}
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{sync_internal 1}
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{sync_external 0}
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{sync_external_cdc 0}} {
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create_bd_cell -type hier $ip_name
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# Control interface
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create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
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create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
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# Device interface
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create_bd_pin -dir I -type clk "${ip_name}/clk"
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create_bd_pin -dir I -type rst "${ip_name}/resetn"
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create_bd_pin -dir I "${ip_name}/sync_in"
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create_bd_pin -dir O "${ip_name}/sync_out"
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for {set i 0} {$i < $num_of_channels} {incr i} {
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create_bd_pin -dir O "${ip_name}/tdd_channel_${i}"
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}
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# Generic TDD core
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ad_ip_instance axi_tdd "${ip_name}/tdd_core" [list \
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CHANNEL_COUNT $num_of_channels \
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DEFAULT_POLARITY $default_polarity \
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REGISTER_WIDTH $reg_counter_width \
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BURST_COUNT_WIDTH $burst_counter_width \
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SYNC_COUNT_WIDTH $sync_counter_width \
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SYNC_INTERNAL $sync_internal \
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SYNC_EXTERNAL $sync_external \
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SYNC_EXTERNAL_CDC $sync_external_cdc
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]
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for {set i 0} {$i < $num_of_channels} {incr i} {
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ad_ip_instance xlslice "${ip_name}/tdd_ch_slice_${i}" [list \
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DIN_WIDTH $num_of_channels \
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DIN_FROM $i \
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DIN_TO $i \
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]
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}
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# Create connections
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ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/tdd_core/s_axi_aclk"
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ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/tdd_core/s_axi_aresetn"
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ad_connect "${ip_name}/s_axi" "${ip_name}/tdd_core/s_axi"
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ad_connect ${ip_name}/tdd_core/clk ${ip_name}/clk
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ad_connect ${ip_name}/tdd_core/resetn ${ip_name}/resetn
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ad_connect ${ip_name}/tdd_core/sync_in ${ip_name}/sync_in
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ad_connect ${ip_name}/tdd_core/sync_out ${ip_name}/sync_out
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for {set i 0} {$i < $num_of_channels} {incr i} {
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ad_connect ${ip_name}/tdd_core/tdd_channel ${ip_name}/tdd_ch_slice_$i/Din
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ad_connect ${ip_name}/tdd_ch_slice_$i/Dout ${ip_name}/tdd_channel_$i
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}
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}
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