93 lines
3.2 KiB
Verilog
Executable File
93 lines
3.2 KiB
Verilog
Executable File
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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reg clk = 1'b0;
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reg [3:0] reset_shift = 4'b1111;
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reg trigger_reset = 1'b0;
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wire reset;
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reg failed = 1'b0;
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reg sysref = 1'b0;
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initial
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begin
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$dumpfile (VCD_FILE);
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$dumpvars;
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`ifdef TIMEOUT
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#`TIMEOUT
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`else
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#100000
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`endif
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if (failed == 1'b0)
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$display("SUCCESS");
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else
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$display("FAILED");
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$finish;
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end
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initial forever #10 clk <= ~clk;
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always @(posedge clk) begin
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if (trigger_reset == 1'b1) begin
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reset_shift <= 3'b111;
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end else begin
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reset_shift <= {reset_shift[2:0],1'b0};
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end
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end
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assign reset = reset_shift[3];
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initial begin
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#1000;
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@(posedge clk) sysref <= 1'b1;
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@(posedge clk) sysref <= 1'b0;
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end
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task do_trigger_reset;
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begin
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@(posedge clk) trigger_reset <= 1'b1;
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@(posedge clk) trigger_reset <= 1'b0;
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end
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endtask
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