Istvan Csomortani 7960b00684 block_design: Update with new clock net variables ... Using the new clock net variables in all Xilinx block designs.		2019-06-11 18:13:06 +03:00
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Makefile	adrv9371: use generic TPL	2019-01-14 17:21:00 +02:00
system_bd.tcl	block_design: Update with new clock net variables	2019-06-11 18:13:06 +03:00
system_constr.xdc	whitespace: Delete all trailing white spaces	2019-06-07 10:20:15 +03:00
system_project.tcl	scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects	2017-06-07 12:06:50 +03:00
system_top.v	all/system_top.v: loopback gpio lines	2018-10-04 14:19:37 +03:00