f22f448d4b
Apparently this constraint will cause more harm than good. The tool will try to prevent an invalid hold violation by increasing the net delay, causing a setup violation on the same path. (inside the smart connect) See more info here: https://forums.xilinx.com/t5/AXI-Infrastructure/Smartconnect-and-Synchronous-Clock-Domain-Crossing-Issues/td-p/904824 |
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| .. | ||
| Makefile | ||
| system_bd.tcl | ||
| system_constr.xdc | ||
| system_project.tcl | ||
| system_top.v | ||