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All input and output delays should be referenced to a virtual clock. If the input and output delays reference base clocks or PLL clocks rather than virtual clocks, the intra- and inter-clock transfer clock uncertainties, determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports. See mnl_timequest_cookbook.pdf for more info. |
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| .. | ||
| a10gx | ||
| common | ||
| kcu105 | ||
| vcu118 | ||
| zc706 | ||
| zcu102 | ||
| Makefile | ||