111 lines
4.3 KiB
Tcl
111 lines
4.3 KiB
Tcl
#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
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# questions about and improve this core. Distribution of source, or resulting
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# binaries (including those inside an FPGA or ASIC) require you to release the
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# source of the entire project (excluding the system libraries provide by the
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License version 2
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# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
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# more information. This commercial license is sub-licensable (if you purchase
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# chips from Analog Devices, incorporate them into your PCB level product, and
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# purchase a JESD204 license, end users of your product will also have a
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
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# or publication in which you use this JESD204 HDL core. (You are not required
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# to do so; it is up to your common sense to decide whether you want to comply
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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# TX interfaces
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adi_if_define "jesd204_tx_cfg"
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adi_if_ports output -1 lanes_disable
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adi_if_ports output -1 links_disable
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adi_if_ports output 8 beats_per_multiframe
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adi_if_ports output 8 octets_per_frame
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adi_if_ports output 8 lmfc_offset
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adi_if_ports output 1 continuous_cgs
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adi_if_ports output 1 continuous_ilas
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adi_if_ports output 1 skip_ilas
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adi_if_ports output 8 mframes_per_ilas
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adi_if_ports output 1 disable_char_replacement
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adi_if_ports output 1 disable_scrambler
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adi_if_define "jesd204_tx_ilas_config"
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adi_if_ports output 1 rd
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adi_if_ports output 2 addr
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adi_if_ports input 32 data
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adi_if_define "jesd204_tx_status"
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adi_if_ports output 1 state
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adi_if_ports output 1 sync
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adi_if_define "jesd204_tx_event"
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adi_if_ports output 1 sysref_alignment_error
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adi_if_ports output 1 sysref_edge
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adi_if_define "jesd204_tx_ctrl"
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adi_if_ports output 1 manual_sync_request
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# RX interfaces
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adi_if_define "jesd204_rx_cfg"
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adi_if_ports output -1 lanes_disable
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adi_if_ports output -1 links_disable
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adi_if_ports output 8 beats_per_multiframe
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adi_if_ports output 8 octets_per_frame
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adi_if_ports output 8 lmfc_offset
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adi_if_ports output 1 buffer_early_release
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adi_if_ports output 1 buffer_delay
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adi_if_ports output 1 disable_char_replacement
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adi_if_ports output 1 disable_scrambler
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adi_if_ports output 1 err_statistics_reset
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adi_if_ports output 3 err_statistics_mask
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adi_if_define "jesd204_rx_status"
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adi_if_ports output 3 ctrl_state
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adi_if_ports output -1 lane_cgs_state
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adi_if_ports output -1 lane_frame_align
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adi_if_ports output -1 lane_ifs_ready
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adi_if_ports output -1 lane_latency_ready
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adi_if_ports output -1 lane_latency
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adi_if_ports output -1 err_statistics_cnt
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adi_if_define "jesd204_rx_ilas_config"
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adi_if_ports output -1 valid
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adi_if_ports output -1 addr
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adi_if_ports input -1 data
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adi_if_define "jesd204_rx_event"
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adi_if_ports output 1 sysref_alignment_error
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adi_if_ports output 1 sysref_edge
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