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pluto_hdl_adi/library/jesd204/jesd204_rx
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Laszlo Nagy b90c2e79dc jesd204_rx: add parameter for input pipeline stages 
Pipeline stages must be implemented on register so placer can spread it
cross the device. Use the shreg_extract attribute to avoid SRL
inference.
 		2019-05-16 13:29:34 +03:00
..
Makefile jesd204_rx/tx: make SYSREF IOB placement optional 2018-07-24 09:16:24 +03:00
align_mux.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
elastic_buffer.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
jesd204_ilas_monitor.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
jesd204_lane_latency_monitor.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
jesd204_rx.v jesd204_rx: add parameter for input pipeline stages 2019-05-16 13:29:34 +03:00
jesd204_rx_cgs.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
jesd204_rx_constr.sdc jesd204: Add Altera/Intel IP support 2017-08-21 11:09:42 +02:00
jesd204_rx_constr.ttcl jesd204_rx/tx: make SYSREF IOB placement optional 2018-07-24 09:16:24 +03:00
jesd204_rx_ctrl.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
jesd204_rx_hw.tcl jesd204_rx: add parameter for input pipeline stages 2019-05-16 13:29:34 +03:00
jesd204_rx_ip.tcl jesd204_rx/tx: make SYSREF IOB placement optional 2018-07-24 09:16:24 +03:00
jesd204_rx_lane.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00