Istvan Csomortani 85f5dc8230 ad9371x/intel: Fix fPLL configuration ... When phase alignment is active, the PFD frequency value should be used as outclk1 actual frequency. The configuration interface of the fPLL does not support fractional values. If the reference clock is fractional, the tool will throw an error that requirement above is not respected. Round up the reference clock for the SERDES and the lane rate in order to overcome this issue, until it's not fixed by Intel.		2021-01-12 19:34:44 +02:00
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adrv9371x_bd.tcl	adrv9371: Add decimation and interpolation filters	2019-08-20 16:24:47 +03:00
adrv9371x_qsys.tcl	ad9371x/intel: Fix fPLL configuration	2021-01-12 19:34:44 +02:00