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Lars-Peter Clausen da28ee3cce axi_ad9361: xilinx LVDS interface: Restore previous feedback clock polarity 
Commit ff50963c7f ("axi_ad9361- altera/xilinx reconcile- may be broken-
do not use") inverted the polarity of the TX feedback clock.

This exposed some issues in the existing drivers which can cause the
interface tuning to fail randomly under certain conditions.

To keep backwards compatibility with existing drivers restore the previous
behavior.

A separate fix will be applied to the drivers that resolves the issue that
has been exposed by the polarity inversion. So that interface calibration
works reliably under all conditions.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2018-01-19 18:17:50 +01:00
library axi_ad9361: xilinx LVDS interface: Restore previous feedback clock polarity 2018-01-19 18:17:50 +01:00
projects adrv9371: Increase FCLK2 to 200MHz to support max sampling rates 2018-01-09 15:20:06 +01:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore 2016-12-19 15:37:05 +00:00
LICENSE license: GPL must be GPL v2 2017-05-31 18:18:45 +03:00
LICENSE_ADIBSD license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_GPL2 license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_LGPL license: Add top level license files 2017-05-29 09:57:39 +03:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

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