d539a8119c
When phase alignment is active, the PFD frequency value should be used as outclk1 actual frequency. The configuration interface of the fPLL does not support fractional values. If the reference clock is fractional, the tool will throw an error that requirement above is not respected. Round up the reference clock for the SERDES and the lane rate in order to overcome this issue, until it's not fixed by Intel. |
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| .. | ||
| a10gx | ||
| a10soc | ||
| common | ||
| s10soc | ||
| zc706 | ||
| zcu102 | ||
| Makefile | ||