240 lines
6.5 KiB
Verilog
Executable File
240 lines
6.5 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad3552r_if_tb;
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parameter VCD_FILE = "axi_ad3552r_if_tb.vcd";
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`define TIMEOUT 9000
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`include "../common/tb/tb_base.v"
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wire [ 23:0] data_read;
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wire dac_sclk;
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wire dac_csn;
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wire dac_data_ready;
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wire [ 3:0] sdio_i;
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wire [ 3:0] sdio_o;
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wire sdio_t;
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wire [31:0] dac_data_final;
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wire [ 3:0] readback_data_shift;
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wire [ 4:0] data_increment_valid;
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wire if_busy;
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reg [ 7:0] address_write = 8'b0;
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reg dac_clk = 1'b0;
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reg reset_in = 1'b1;
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reg transfer_data = 1'b0;
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reg sdr_ddr_n = 1'b1;
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reg reg_8b_16bn = 1'b0;
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reg stream = 1'b0;
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reg [23:0] data_write = 24'h0;
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reg dac_data_valid = 1'b0;
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reg [ 3:0] shift_count = 4'b0;
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reg [31:0] transfer_reg = 32'h89abcdef;
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reg [ 4:0] valid_counter = 5'b0;
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reg [31:0] dac_data = 32'b0;
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always #4 dac_clk <= ~dac_clk;
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initial begin
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#100 reset_in = 1'b0;
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// Write 8 bit SDR
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address_write = 8'h2c;
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data_write = 24'hab0000;
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sdr_ddr_n = 1'b1;
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reg_8b_16bn = 1'b1;
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stream = 1'b0;
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#500 transfer_data = 1'b1;
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#100 transfer_data = 1'b0;
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// Read 8 bit SDR
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address_write = 8'hac;
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data_write = 24'h000000;
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sdr_ddr_n = 1'b1;
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reg_8b_16bn = 1'b1;
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stream = 1'b0;
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#500 transfer_data = 1'b1;
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#100 transfer_data = 1'b0;
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// Write 16 bit SDR
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address_write = 8'h2c;
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data_write = 24'h123400;
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sdr_ddr_n = 1'b1;
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reg_8b_16bn = 1'b0;
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stream = 1'b0;
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#500 transfer_data = 1'b1;
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#100 transfer_data = 1'b0;
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// Read 16 bit SDR
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address_write = 8'hac;
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data_write = 24'h000000;
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sdr_ddr_n = 1'b1;
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reg_8b_16bn = 1'b0;
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stream = 1'b0;
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#500 transfer_data = 1'b1;
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#100 transfer_data = 1'b0;
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#500;
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// Write 8 bit DDR
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address_write = 8'h2c;
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data_write = 24'h120000;
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sdr_ddr_n = 1'b0;
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reg_8b_16bn = 1'b1;
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stream = 1'b0;
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#500 transfer_data = 1'b1;
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#100 transfer_data = 1'b0;
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// Read 8 bit DDR
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address_write = 8'hac;
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data_write = 24'h000000;
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sdr_ddr_n = 1'b0;
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reg_8b_16bn = 1'b1;
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stream = 1'b0;
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#500 transfer_data = 1'b1;
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#100 transfer_data = 1'b0;
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// Write 16 bit DDR
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address_write = 8'h2c;
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data_write = 24'h123400;
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sdr_ddr_n = 1'b0;
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reg_8b_16bn = 1'b0;
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stream = 1'b0;
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transfer_data = 1'b1;
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#100 transfer_data = 1'b0;
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// Read 16 bit DDR
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address_write = 8'hac;
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data_write = 24'h000000;
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sdr_ddr_n = 1'b0;
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reg_8b_16bn = 1'b0;
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stream = 1'b0;
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#500 transfer_data = 1'b1;
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#100 transfer_data = 1'b0;
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#500;
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// Stream SDR
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address_write = 8'h2c;
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sdr_ddr_n = 1'b1;
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reg_8b_16bn = 1'b0;
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stream = 1'b1;
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transfer_data = 1'b1;
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#100 transfer_data = 1'b0;
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#1000 stream = 1'b0;
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#500;
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// Stream DDR
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address_write = 8'h2c;
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reg_8b_16bn = 1'b1;
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sdr_ddr_n = 1'b0;
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stream = 1'b1;
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transfer_data = 1'b1;
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#100 transfer_data = 1'b0;
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#1000 stream = 1'b0;
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end
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// data is incremented at each complete cycle
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assign dac_data_final = (stream == 1'b1) ? dac_data : data_write;
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assign data_increment_valid = (sdr_ddr_n ) ? 5'd16: 5'h8;
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always @(posedge dac_clk) begin
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if (valid_counter == data_increment_valid) begin
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dac_data <= dac_data + 32'h00010002;
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valid_counter <= 3'b0;
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dac_data_valid <= 1'b1;
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end else begin
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dac_data <= dac_data;
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valid_counter <= valid_counter + 3'b1;
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dac_data_valid <= 1'b0;
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end
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end
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// data is circullary shifted at every sampling edge
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assign readback_data_shift = (sdr_ddr_n ) ? 4'h8 : 4'h4;
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assign sdio_i = (sdio_t === 1'b1) ? transfer_reg[31:28] : 4'b0;
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always @(posedge dac_clk) begin
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if (shift_count == readback_data_shift) begin
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transfer_reg <= {transfer_reg[27:0],transfer_reg[31:28]};
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end else if (sdio_t === 1'b1) begin
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transfer_reg <= transfer_reg;
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end
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if (shift_count == readback_data_shift || dac_csn == 1'b1) begin
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shift_count <= 3'b0;
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end else if (sdio_t === 1'b1) begin
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shift_count <= shift_count + 3'b1;
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end
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end
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axi_ad3552r_if axi_ad3552r_interface (
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.clk_in(dac_clk),
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.reset_in(reset_in),
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.dac_data(dac_data_final),
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.dac_data_valid(dac_data_valid),
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.address(address_write),
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.data_read(data_read),
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.data_write(data_write),
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.sdr_ddr_n(sdr_ddr_n),
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.symb_8_16b(reg_8b_16bn),
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.transfer_data(transfer_data),
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.stream(stream),
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.dac_data_ready(dac_data_ready),
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.if_busy(if_busy),
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.sclk(dac_sclk),
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.csn(dac_csn),
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.sdio_i(sdio_i),
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.sdio_o(sdio_o),
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.sdio_t(sdio_t));
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endmodule
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