108 lines
4.9 KiB
Plaintext
108 lines
4.9 KiB
Plaintext
###############################################################################
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## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./" :>
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<: setFileName [ttcl_add $ComponentName "_constr"] :>
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<: setFileExtension ".xdc" :>
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<: setFileProcessingOrder late :>
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<: set tdd_sync_int [get_property MODELPARAM_VALUE.SYNC_INTERNAL] :>
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<: set tdd_sync_ext [get_property MODELPARAM_VALUE.SYNC_EXTERNAL] :>
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<: set tdd_sync_cdc [get_property MODELPARAM_VALUE.SYNC_EXTERNAL_CDC] :>
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<: set tdd_sync_width [get_property MODELPARAM_VALUE.SYNC_COUNT_WIDTH] :>
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set_property ASYNC_REG TRUE \
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[get_cells -hier {*cdc_sync_stage1_reg*}] \
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[get_cells -hier {*cdc_sync_stage2_reg*}]
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<: if { $tdd_sync_cdc == 1 } { :>
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set_property ASYNC_REG TRUE \
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[get_cells -hier {*tdd_sync_m1_reg*}] \
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[get_cells -hier {*tdd_sync_m2_reg*}] \
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[get_cells -hier {*tdd_sync_m3_reg*}]
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set_false_path -to [get_cells -hierarchical * -filter {NAME=~*i_sync_gen/tdd_sync_m1_reg}]
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<: } :>
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_burst_count_reg[*]}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_counter/tdd_burst_count_reg[*]}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_startup_delay_reg[*]}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_counter/tdd_startup_delay_reg[*]}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_frame_length_reg[*]}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_counter/tdd_frame_length_reg[*]}]
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<: if { $tdd_sync_width > 0 } { :>
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_period_low_reg[*]}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_sync_gen/tdd_sync_period_reg[*]}]
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<: } :>
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<: if { $tdd_sync_width > 32 } { :>
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_period_high_reg[*]}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_sync_gen/tdd_sync_period_reg[*]}]
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<: } :>
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_channel_pol_reg[*]}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_channel/ch_pol_reg}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*up_tdd_channel_on_reg[*][*]}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_channel/t_high_reg[*]}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*up_tdd_channel_off_reg[*][*]}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_channel/t_low_reg[*]}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_enable_reg}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[0]}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_rst_reg}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[1]}]
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<: if { $tdd_sync_int == 1 } { :>
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_int_reg}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[2]}]
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<: } :>
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<: if { $tdd_sync_ext == 1 } { :>
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_ext_reg}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[3]}]
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<: } :>
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_channel_en_reg[*]}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_ch_en_sync/cdc_sync_stage1_reg[*]}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/cdc_hold_reg*}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/out_data_reg*}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/in_toggle_d1_reg}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/i_sync_out/cdc_sync_stage1_reg[*]}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/out_toggle_d1_reg}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/i_sync_in/cdc_sync_stage1_reg[*]}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/in_toggle_d1_reg}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/i_sync_out/cdc_sync_stage1_reg[*]}]
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/out_toggle_d1_reg}] \
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-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/i_sync_in/cdc_sync_stage1_reg[*]}]
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