449 lines
16 KiB
Tcl
449 lines
16 KiB
Tcl
###############################################################################
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## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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## Define an interface for Platform Designer.
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#
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# \param[type] - Type of the interface, valid values are : clock, reset, reset-n,
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# signal, intr
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# \param[name] - The name of the interface
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# \param[dir] - The direction of the interface
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# \param[width] - The width of the interface
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# \param[arg_1] - Optional argument to define the associated clock for a reset
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# interface
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# \param[arg_2] - Optional argument to define the associated reset sink for a
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# reset interface
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#
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proc ad_interface {type name dir width {arg_1 ""} {arg_2 ""}} {
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if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "input"])} {
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add_interface if_${name} clock sink
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add_interface_port if_${name} ${name} clk ${dir} ${width}
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return
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}
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if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "output"])} {
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add_interface if_${name} clock source
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add_interface_port if_${name} ${name} clk ${dir} ${width}
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return
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}
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if {([string equal -nocase ${type} "reset"]) && ([string equal -nocase ${dir} "input"])} {
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add_interface if_${name} reset sink
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add_interface_port if_${name} ${name} reset ${dir} ${width}
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set_interface_property if_${name} associatedclock ${arg_1}
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return
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}
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if {([string equal -nocase ${type} "reset"]) && ([string equal -nocase ${dir} "output"])} {
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add_interface if_${name} reset source
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add_interface_port if_${name} ${name} reset ${dir} ${width}
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set_interface_property if_${name} associatedclock ${arg_1}
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set_interface_property if_${name} associatedResetSinks ${arg_2}
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return
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}
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if {([string equal -nocase ${type} "reset-n"]) && ([string equal -nocase ${dir} "input"])} {
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add_interface if_${name} reset sink
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add_interface_port if_${name} ${name} reset_n ${dir} ${width}
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set_interface_property if_${name} associatedclock ${arg_1}
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return
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}
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if {([string equal -nocase ${type} "reset-n"]) && ([string equal -nocase ${dir} "output"])} {
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add_interface if_${name} reset source
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add_interface_port if_${name} ${name} reset_n ${dir} ${width}
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set_interface_property if_${name} associatedclock ${arg_1}
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set_interface_property if_${name} associatedResetSinks ${arg_2}
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return
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}
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if {([string equal -nocase ${type} "intr"]) && ([string equal -nocase ${dir} "output"])} {
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add_interface if_${name} interrupt source
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add_interface_port if_${name} ${name} irq ${dir} ${width}
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set_interface_property if_${name} associatedclock ${arg_1}
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return
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}
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set remap $arg_1
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if {$arg_1 eq ""} {
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set remap $name
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}
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if {[string equal -nocase ${type} "signal"]} {
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add_interface if_${name} conduit end
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add_interface_port if_${name} ${name} ${remap} ${dir} ${width}
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return
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}
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}
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## Create a point-to-point conduit interface.
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#
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# \param[if_name] - the name of the interface
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# \param[if_port] - the type of signal for this port, which must be unique
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# \param[port] - the name of the port, this name must match the signal name
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# in HDL
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# \param[dir] - the direction of the signal, expected values: input/output/bidir
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# \param[width] - the width of the port, in bits
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#
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proc ad_conduit {if_name if_port port dir width} {
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add_interface $if_name conduit end
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add_interface_port $if_name $port $if_port $dir $width
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}
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## Create an IP.
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#
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# \param[pname] - name of the IP, general equivalent to the top HDL module name
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# \param[pdisplay_name] - displayed name
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# \param[pelabfunction] - name of the elaboration callback function
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# \param[pcomposefunction] - name of the composition callback function
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#
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proc ad_ip_create {pname pdisplay_name {pelabfunction ""} {pcomposefunction ""}} {
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set_module_property NAME $pname
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set_module_property DISPLAY_NAME $pdisplay_name
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set_module_property DESCRIPTION $pdisplay_name
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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if {$pelabfunction ne ""} {
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set_module_property ELABORATION_CALLBACK $pelabfunction
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}
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if {$pcomposefunction ne ""} {
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set_module_property COMPOSITION_CALLBACK $pcomposefunction
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}
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}
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## Create an IP parameter.
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#
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# \param[pname] - name of the IP, general equivalent to the top HDL module name
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# \param[ptype] - the data type of the parameter
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# \param[pdefault] - the initial value of the parameter
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# \param[phdl] - define if the parameter is an HDL parameter or not
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# \param[properties] - can define different properties for the parameter, must be
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# a list of {key, value} pairs
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#
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proc ad_ip_parameter {pname ptype pdefault {phdl true} {properties {}}} {
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if {$pname eq "DEVICE_FAMILY"} {
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add_parameter DEVICE_FAMILY STRING
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set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
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set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
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set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
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set_parameter_property DEVICE_FAMILY ENABLED true
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} else {
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add_parameter $pname $ptype $pdefault
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set_parameter_property $pname HDL_PARAMETER $phdl
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set_parameter_property $pname ENABLED true
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}
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foreach {key value} $properties {
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set_parameter_property $pname $key $value
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}
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}
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## Adds the generic ADI spec parameters to the current IP, with the help of
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# adi_add_device_spec_param. The spec parameter list is auto_gen_param_list,
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# from library/scripts/adi_intel_device_info_enc.tcl.
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#
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proc adi_add_auto_fpga_spec_params {} {
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global ad_hdl_dir
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source $ad_hdl_dir/library/scripts/adi_intel_device_info_enc.tcl
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ad_ip_parameter DEVICE STRING "" false {
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SYSTEM_INFO DEVICE
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VISIBLE false
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}
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foreach p $auto_gen_param_list {
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adi_add_device_spec_param $p
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}
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}
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## Generate validation properties for a parameter, using predefined ranges or
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# set of values (the definition of the ranges can be found in
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# library/scripts/adi_intel_device_info_enc.tcl).
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#
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# In Intel callback flow, one cannot directly change a parameter value, the value
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# can only be calculated/deduced from the environment.
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# Adding a second parameter with the same name followed by "_MANUAL", will add
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# in the environment the desired value that is still constrained to a predefined
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# set. Having the second parameter is not enough, to activate the manual
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# overwriting of a parameter one must call the adi_add_indep_spec_params_overwrite
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# process.
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#
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# \param[param] - Name of the HDL parameter. The list of accepted values for
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# the parameter are defined with the same name as the parameter's one(lower case),
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# followed by "_list"
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#
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proc adi_add_device_spec_param {param} {
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global auto_gen_param_list
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global auto_set_param_list
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global fpga_technology_list
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global fpga_family_list
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global speed_grade_list
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global dev_package_list
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global xcvr_type_list
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global fpga_voltage_list
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set group "FPGA info"
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set list_pointer [string tolower $param]
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set list_pointer [append list_pointer "_list"]
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set enc_list [subst $$list_pointer]
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set ranges ""
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add_parameter $param INTEGER
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set_parameter_property $param DISPLAY_NAME $param
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set_parameter_property $param GROUP $group
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set_parameter_property $param UNITS None
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set_parameter_property $param HDL_PARAMETER true
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set_parameter_property $param VISIBLE true
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set_parameter_property $param DERIVED true
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add_parameter ${param}_MANUAL INTEGER
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set_parameter_property ${param}_MANUAL DISPLAY_NAME $param
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set_parameter_property ${param}_MANUAL GROUP $group
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set_parameter_property ${param}_MANUAL UNITS None
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set_parameter_property ${param}_MANUAL HDL_PARAMETER false
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set_parameter_property ${param}_MANUAL VISIBLE false
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set_parameter_property ${param}_MANUAL DEFAULT_VALUE [lindex $enc_list 0 1]
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foreach i $enc_list {
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set value [lindex $i 0]
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set encode [lindex $i 1]
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append ranges "\"$encode\:$value\" "
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}
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set_parameter_property $param ALLOWED_RANGES $ranges
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set_parameter_property ${param}_MANUAL ALLOWED_RANGES $ranges
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}
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## Creates a boolean type parameter that allows this user to manually overwrite
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# parameter values.
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#
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# \param[param] - Name of the HDL parameter.
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#
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proc adi_add_indep_spec_params_overwrite {param} {
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add_parameter ${param}_USER_OVERWRITE BOOLEAN 0
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set_parameter_property ${param}_USER_OVERWRITE DISPLAY_NAME "Manually overwrite $param parameter"
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set_parameter_property ${param}_USER_OVERWRITE HDL_PARAMETER false
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set_parameter_property ${param}_USER_OVERWRITE GROUP {FPGA info}
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}
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## In this process the IP parameters are compared against predefined parameter lists
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# in library/scripts/adi_intel_device_info_enc.tcl. For the matching parameters,
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# a search is started after a pair *_USER_OVERWRITE(boolean) parameter. If the pair
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# *_USER_OVERWRITE parameter is found, and its value is true, the target parameter
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# will take the value of the *_MANUAL parameter. The GUI parameter is set as
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# writable in the qsys GUI (${parameter_name} is replaced by ${parameter_name}_MANUAL).
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#
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proc info_param_validate {} {
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global ad_hdl_dir
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global fpga_technology
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global fpga_family
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global speed_grade
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global dev_package
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global xcvr_type
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global fpga_voltage
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source $ad_hdl_dir/library/scripts/adi_intel_device_info_enc.tcl
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set device [get_parameter_value DEVICE]
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set auto_populate true ;# for future code dev
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set all_ip_param_list [get_parameters]
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set validate_list ""
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set independent_overwrite_list ""
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foreach param $all_ip_param_list {
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foreach elem [concat $auto_gen_param_list $auto_set_param_list] {
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if { "$elem" == "$param" } {
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append validate_list "$param "
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}
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if { [regexp ${elem}_USER_OVERWRITE $param] } {
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append independent_overwrite_list "$elem "
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}
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}
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}
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set indep_overwrite [expr {[llength $independent_overwrite_list] != 0} ? 1 : 0]
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if { $auto_populate == true } {
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get_part_param ;# in adi_intel_device_info_enc.tcl
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# point parameters and assign
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foreach param $validate_list {
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set ls_param [string tolower $param]
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set list_pointer $ls_param
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append list_pointer "_list"
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set pointer_to_sys_val [subst $$ls_param] ;# e.g., $fpga_technology
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set enc_list_pointer [subst $$list_pointer] ;# e.g., $fpga_technology_list
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# get_part_info returns '{'#value'}'
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regsub -all "{" $pointer_to_sys_val "" pointer_to_sys_val
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regsub -all "}" $pointer_to_sys_val "" pointer_to_sys_val
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# the list defines a range or pairs of values
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set get_list_correspondence 1
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if { [llength $enc_list_pointer] != 0 } {
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if { [llength $enc_list_pointer] == 2 } {
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if { [llength [lindex $enc_list_pointer 0]] == 1 } {
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set get_list_correspondence 0
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}
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}
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} else {
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send_message ERROR "No list $list_pointer defined in adi_intel_device_info_enc.tcl for parameter $param"
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}
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# auto assign parameter value
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if { $get_list_correspondence } {
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set matched ""
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foreach i $enc_list_pointer {
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if { [regexp ^[lindex $i 0] $pointer_to_sys_val] } {
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set matched [lindex $i 1]
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}
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}
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if { $matched == "" } {
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send_message ERROR "Unknown or undefined(adi_intel_device_info_enc.tcl) $param \"$pointer_to_sys_val\" form \"$device\" device"
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} else {
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set_parameter_value $param $matched
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}
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} else {
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set_parameter_value $param $pointer_to_sys_val
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}
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}
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} else {
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foreach p $validate_list {
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set_parameter_value $p [get_parameter_value ${p}_MANUAL]
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}
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}
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# display manual(writable) or auto(non-writable) parameters
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foreach p $validate_list {
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set_parameter_property ${p}_MANUAL VISIBLE [expr $auto_populate ? false : true]
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set_parameter_property $p VISIBLE $auto_populate
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if { $indep_overwrite == 1 } {
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foreach p_overwrite $independent_overwrite_list {
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if { $p == $p_overwrite } {
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set p_over_val [get_parameter_value ${p}_USER_OVERWRITE]
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# set the hdl parameter with the independent manual overwritten value
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if { $p_over_val } {
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set_parameter_value $p [get_parameter_value ${p}_MANUAL]
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set_parameter_property ${p}_MANUAL VISIBLE $p_over_val
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set_parameter_property $p VISIBLE [expr $p_over_val ? false : true]
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}
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}
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}
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}
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}
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}
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## Add source files to an IP, automatically find the file type using its extension.
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#
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# \param[pname] - name of the IP, general equivalent to the top HDL module name
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# \param[pfile] - name of the file
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#
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proc ad_ip_addfile {pname pfile} {
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set pmodule [file tail $pfile]
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regsub {\..$} $pmodule {} mname
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if {$pname eq $mname} {
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add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
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return
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}
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set ptype [file extension $pfile]
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if {$ptype eq ".v"} {
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add_fileset_file $pmodule VERILOG PATH $pfile
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return
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}
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if {$ptype eq ".sv"} {
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add_fileset_file $pmodule SYSTEM_VERILOG PATH $pfile
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return
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}
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if {$ptype eq ".vh"} {
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add_fileset_file $pmodule VERILOG_INCLUDE PATH $pfile
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return
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}
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if {$ptype eq ".svh"} {
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add_fileset_file $pmodule SYSTEM_VERILOG_INCLUDE PATH $pfile
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return
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}
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if {$ptype eq ".sdc"} {
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add_fileset_file $pmodule SDC PATH $pfile
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return
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}
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if {$ptype eq ".tcl"} {
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add_fileset_file $pmodule OTHER PATH $pfile
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return
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}
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}
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## Add source files to an IP, automatically find the file type using its extension.
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#
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# \param[pname] - name of the IP, general equivalent to the top HDL module name
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# \param[pfile] - name of the file
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#
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proc ad_ip_files {pname pfiles {pfunction ""}} {
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add_fileset quartus_synth QUARTUS_SYNTH $pfunction ""
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set_fileset_property quartus_synth TOP_LEVEL $pname
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foreach pfile $pfiles {
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ad_ip_addfile $pname $pfile
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}
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add_fileset quartus_sim SIM_VERILOG $pfunction ""
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set_fileset_property quartus_sim TOP_LEVEL $pname
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foreach pfile $pfiles {
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ad_ip_addfile $pname $pfile
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}
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}
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## Infer an AXI4 Lite memory mapped interface.
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#
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# \param[aclk] - name of the interface clock
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# \param[arstn] - name fo the interface reset
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# \param[addr_width] - address width of the read and write channels
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#
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proc ad_ip_intf_s_axi {aclk arstn {addr_width 16}} {
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add_interface s_axi_clock clock end
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add_interface_port s_axi_clock ${aclk} clk Input 1
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add_interface s_axi_reset reset end
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set_interface_property s_axi_reset associatedClock s_axi_clock
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add_interface_port s_axi_reset ${arstn} reset_n Input 1
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add_interface s_axi axi4lite end
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set_interface_property s_axi associatedClock s_axi_clock
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set_interface_property s_axi associatedReset s_axi_reset
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add_interface_port s_axi s_axi_awvalid awvalid Input 1
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add_interface_port s_axi s_axi_awaddr awaddr Input $addr_width
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add_interface_port s_axi s_axi_awprot awprot Input 3
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add_interface_port s_axi s_axi_awready awready Output 1
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add_interface_port s_axi s_axi_wvalid wvalid Input 1
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add_interface_port s_axi s_axi_wdata wdata Input 32
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add_interface_port s_axi s_axi_wstrb wstrb Input 4
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add_interface_port s_axi s_axi_wready wready Output 1
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add_interface_port s_axi s_axi_bvalid bvalid Output 1
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add_interface_port s_axi s_axi_bresp bresp Output 2
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add_interface_port s_axi s_axi_bready bready Input 1
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add_interface_port s_axi s_axi_arvalid arvalid Input 1
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add_interface_port s_axi s_axi_araddr araddr Input $addr_width
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add_interface_port s_axi s_axi_arprot arprot Input 3
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add_interface_port s_axi s_axi_arready arready Output 1
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add_interface_port s_axi s_axi_rvalid rvalid Output 1
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add_interface_port s_axi s_axi_rresp rresp Output 2
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add_interface_port s_axi s_axi_rdata rdata Output 32
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add_interface_port s_axi s_axi_rready rready Input 1
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}
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