99 lines
3.1 KiB
Verilog
99 lines
3.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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//
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// Simple pulse generator for TDD control
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// The module has two modes. In function of the state of sync_mode,
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// the syncronization signal (sync_out) can get its value from an external
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// source or from its internal generator.
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//
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`timescale 1ns/1ps
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module util_tdd_sync #(
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parameter TDD_SYNC_PERIOD = 100000000
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) (
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input clk,
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input rstn,
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input sync_mode,
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input sync_in,
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output reg sync_out
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);
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reg sync_mode_d1 = 1'b0;
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reg sync_mode_d2 = 1'b0;
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wire sync_internal;
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wire sync_external;
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// pulse generator
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util_pulse_gen #(
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.PULSE_PERIOD(TDD_SYNC_PERIOD)
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) i_tdd_sync (
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.clk (clk),
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.rstn (rstn),
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.pulse_width (32'd0),
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.pulse_period (32'd0),
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.load_config (1'd0),
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.pulse (sync_internal));
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// synchronization logic
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always @(posedge clk) begin
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if(rstn == 1'b0) begin
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sync_mode_d1 <= 1'b0;
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sync_mode_d2 <= 1'b0;
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end else begin
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sync_mode_d1 <= sync_mode;
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sync_mode_d2 <= sync_mode_d1;
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end
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end
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// output logic
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assign sync_external = sync_in;
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always @(posedge clk) begin
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if(rstn == 1'b0) begin
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sync_out <= 1'b0;
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end else begin
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sync_out <= (sync_mode_d2 == 1'b0) ? sync_internal : sync_external;
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end
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end
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endmodule
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