612 lines
14 KiB
Plaintext
612 lines
14 KiB
Plaintext
TITLE
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HDMI Transmit (axi_hdmi_tx)
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HDMI_TX
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x0010
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REG_RSTN
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[0] 0x0
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RSTN
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RW
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Reset, a common reset is used for all the interface modules,
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The default is reset (0x0), software must write 0x1 to bring up the core.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0011
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REG_CNTRL1
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[2] 0x0
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SS_BYPASS
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RW
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If set (0x1) bypasses the chroma sub-sampler. This is primarily intended to be used to send
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the test-pattern directly to the HDMI transmitter without modifying it.
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ENDFIELD
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FIELD
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[1] 0x0
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RESERVED
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RO
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Reserved
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ENDFIELD
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FIELD
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[0] 0x0
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CSC_BYPASS
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RW
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If set (0x1) bypasses color space conversion (if equipped). And depending on its value, the
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default value of color space boundaries is set in the REG_CLIPP_MAX and REG_CLIPP_MIN registers.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0012
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REG_CNTRL2
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[1:0] 0x0
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SOURCE_SEL
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RW
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Select the HDMI data source- register constant (0x3), incr-pattern (0x2),
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input (0x1) or disabled (0x0).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0013
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REG_CNTRL3
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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CONST_RGB[23:0]
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RW
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This is the RGB value transmitted, if the source is constant (see above).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0015
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REG_CLK_FREQ
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[31:0] 0x00000000
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CLK_FREQ[31:0]
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RO
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Interface clock frequency. This is relative to the processor clock and in many cases is
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100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
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clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock
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is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be
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the same as the interface clock- software must consider device specific implementation
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parameters to calculate the final sampling clock.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0016
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REG_CLK_RATIO
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[31:0] 0x00000000
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CLK_RATIO[31:0]
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RO
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Interface clock ratio - as a factor actual received clock. This is implementation specific
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and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0017
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REG_STATUS
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ADC Interface Control & Status
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ENDREG
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FIELD
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[0] 0x0
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STATUS
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RO
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Interface status, if set indicates no errors. If not set, there
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are errors, software may try resetting the cores.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0018
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REG_VDMA_STATUS
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[1] 0x0
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VDMA_OVF
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RW1C
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If set, indicates vdma overflow.
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ENDFIELD
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FIELD
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[0] 0x0
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VDMA_UNF
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RW1C
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If set, indicates vdma underflow.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0019
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REG_TPM_STATUS
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[1] 0x0
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HDMI_TPM_OOS
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RW1C
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If set, indicates TPM OOS at the HDMI interface.
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ENDFIELD
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FIELD
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[0] 0x0
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VDMA_TPM_OOS
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RW1C
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If set, indicates TPM OOS at the VDMA interface.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001a
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REG_CLIPP_MAX
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[23:16] 0xF0
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R_MAX/Cr_MAX
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RW
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Defines the maximum value for clipping the red or red-difference chroma component.
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Default value are 0xf0 for red-difference chroma and 0xfe for red.
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ENDFIELD
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FIELD
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[16:8] 0xEB
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G_MAX/Y_MAX
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RW
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Defines the maximum value for clipping the green or luma component.
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Default values are 0xeb for luma and and 0xfe for green.
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ENDFIELD
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FIELD
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[7:0] 0xF0
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B_MAX/Cb_MAX
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RW
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Defines the maximum value for clipping the blue or blue-difference chroma component.
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Default value are 0xf0 for blue-difference chroma and 0xfe for blue.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001b
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REG_CLIPP_MIN
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[23:16] 0x10
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R_MIN/Cr_MIN
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RW
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Defines the minimum value for clipping the red or red-difference chroma component.
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Default value are 0x10 for red-difference chroma and 0x01 for red.
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ENDFIELD
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FIELD
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[16:8] 0x10
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G_MIN/Y_MIN
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RW
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Defines the minimum value for clipping the green or luma component.
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Default values are 0x10 for luma and and 0x01 for green.
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ENDFIELD
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FIELD
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[7:0] 0x10
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B_MIN/Cb_MIN
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RW
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Defines the minimum value for clipping the blue or blue-difference chroma component.
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Default value are 0x10 for blue-difference chroma and 0x01 for blue.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0100
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REG_HSYNC_1
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[31:16] 0x0000
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H_LINE_ACTIVE[15:0]
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RW
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This is the horizontal line active pixel width (active resolution length). e.g. 1920 (1080p)
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ENDFIELD
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FIELD
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[15:0] 0x0000
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H_LINE_WIDTH[15:0]
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RW
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This is the horizontal line width (no. of pixel clocks per line). e.g. 2200 (1080p)
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0101
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REG_HSYNC_2
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[15:0] 0x0000
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H_SYNC_WIDTH[15:0]
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RW
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This is the horizontal sync width (no. of pixel clocks). e.g. 44 (1080p)
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0102
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REG_HSYNC_3
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[31:16] 0x0000
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H_ENABLE_MAX[15:0]
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RW
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This is the horizontal data enable maximum. It is the sum of H_ENABLE_MIN and the active
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pixel width. e.g. 2112 (192 + 1920) (1080p)
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ENDFIELD
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FIELD
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[15:0] 0x0000
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H_ENABLE_MIN[15:0]
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RW
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This is the horizontal data enable minimum. It is the sum of horizontal back porch (number
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of clock cycles between the falling edge of HSYNC to the rising edge of DE) and the sync
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width. e.g. 192 (44 + 148) (1080p)
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0110
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REG_VSYNC_1
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[31:16] 0x0000
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V_FRAME_ACTIVE[15:0]
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RW
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This is the vertical frame active line width (active resolution height). e.g. 1080 (1080p)
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ENDFIELD
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FIELD
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[15:0] 0x0000
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V_FRAME_WIDTH[15:0]
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RW
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This is the vertical frame width (no. of lines per frame). e.g. 1125 (1080p)
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0111
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REG_VSYNC_2
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[15:0] 0x0000
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V_SYNC_WIDTH[15:0]
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RW
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This is the vertical sync width (no. of lines). e.g. 5 (1080p)
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0112
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REG_VSYNC_3
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[31:16] 0x0000
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V_ENABLE_MAX[15:0]
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RW
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This is the vertical data enable maximum. It is the sum of V_ENABLE_MIN and the active
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pixel height. e.g. 1121 (41 + 1080) (1080p)
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ENDFIELD
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FIELD
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[15:0] 0x0000
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V_ENABLE_MIN[15:0]
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RW
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This is the vertical data enable minimum. It is the sum of vertical back porch (number of lines
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between the falling edge of VSYNC to the rising edge of DE) and the sync width.
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e.g. 41 (36 + 5) (1080p)
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ENDFIELD
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############################################################################################
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############################################################################################
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TITLE
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HDMI Receive (axi_hdmi_rx)
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hdmi_rx
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x0010
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REG_RSTN
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[0] 0x0
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RSTN
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RW
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Reset, a common reset is used for all the interface modules,
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The default is reset (0x0), software must write 0x1 to bring up the core.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0011
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REG_CNTRL
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[3] 0x0
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EDGE_SEL
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RW
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If set (0x1), incoming data is registered on the falling edge of the clock first. The
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default uses rising edge.
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ENDFIELD
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FIELD
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[2] 0x0
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BGR
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RW
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If set (0x1), output BGR. The default is RGB.
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ENDFIELD
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FIELD
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[1] 0x0
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PACKED
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RW
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If set (0x1) pack 24bit RGB data on 32bit dwords. The default pads the MSB to zeros.
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ENDFIELD
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FIELD
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[0] 0x0
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CSC_BYPASS
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RW
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If set (0x1) bypasses color space conversion (if equipped).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0015
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REG_CLK_FREQ
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[31:0] 0x00000000
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CLK_FREQ[31:0]
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RO
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Interface clock frequency. This is relative to the processor clock and in many cases is
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100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
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clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock
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is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be
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the same as the interface clock- software must consider device specific implementation
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parameters to calculate the final sampling clock.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0016
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REG_CLK_RATIO
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[31:0] 0x00000000
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CLK_RATIO[31:0]
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RO
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Interface clock ratio - as a factor actual received clock. This is implementation specific
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and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0018
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REG_VDMA_STATUS
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[1] 0x0
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VDMA_OVF
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RW1C
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If set, indicates vdma overflow.
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ENDFIELD
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FIELD
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[0] 0x0
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VDMA_UNF
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RW1C
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If set, indicates vdma underflow.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0019
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REG_TPM_STATUS1
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[1] 0x0
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HDMI_TPM_OOS
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RW1C
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If set, indicates TPM OOS at the HDMI interface.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0020
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REG_TPM_STATUS2
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[3] 0x0
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VS_OOS
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RW1C
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If set, indicates VSYNC OOS - the core is unabled to detect/track VSYNC. Consecutive frames have different number of lines.
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ENDFIELD
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FIELD
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[2] 0x0
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HS_OOS
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RW1C
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If set, indicates HSYNC OOS - the core is unabled to detect/track HSYNC. Consecutive lines have different lengths.
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ENDFIELD
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FIELD
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[1] 0x0
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VS_MISMATCH
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RW1C
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If set, indicates received (detected) & programmed VSYNC (number of lines) mismatch. Incoming frames are stable but not the expected resolution.
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ENDFIELD
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FIELD
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[0] 0x0
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HS_MISMATCH
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RW1C
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If set, indicates received (detected) & programmed HSYNC (number of pixels) mismatch. Incoming frames are stable but not the expected resolution.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0100
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REG_HVCOUNTS1
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[31:16] 0x0000
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VS_COUNT[15:0]
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RW
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This is the expected active horizontal pixel lines (active resolution length). e.g. 1080 (1080p)
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ENDFIELD
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FIELD
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[15:0] 0x0000
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HS_COUNT[15:0]
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RW
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This is the expected horizontal pixel count (no. of pixel clocks per line). e.g. 1920 (1080p)
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0101
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REG_HVCOUNTS2
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HDMI Interface Control & Status
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ENDREG
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FIELD
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[31:16] 0x0000
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VS_COUNT[15:0]
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RO
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This is the detected horizontal active pixel lines (active resolution length).
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This field is valid only if VS_OOS is zero.
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ENDFIELD
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FIELD
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[15:0] 0x0000
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HS_COUNT[15:0]
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RO
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This is the detected horizontal pixel count (no. of pixel clocks per line).
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This field is valid only if HS_OOS is zero.
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ENDFIELD
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############################################################################################
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############################################################################################
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